[PATCH 08/13] drm/amd/powerplay: correct smc display config setting
Alex Deucher
alexdeucher at gmail.com
Tue Jun 19 15:13:21 UTC 2018
On Tue, Jun 19, 2018 at 3:39 AM, Evan Quan <evan.quan at amd.com> wrote:
> Multi monitor situation should be taked into consideration.
> Also, there is no need to setup UCLK hard min clock level.
This looks like it should be two patches since there are two distinct
changes. Also please extend the commit messages a bit (e.g., "need to
take into account multi-head with synced displays" and "we don't need
to set a uclk hard min because..."). With that fixed:
Acked-by: Alex Deucher <alexander.deucher at amd.com>
>
> Change-Id: Icf1bc9b420a40433338d9071e386308d30999491
> Signed-off-by: Evan Quan <evan.quan at amd.com>
> ---
> drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c | 13 ++-----------
> 1 file changed, 2 insertions(+), 11 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
> index cb0589e..4732179 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
> @@ -1399,9 +1399,9 @@ static int vega12_notify_smc_display_config_after_ps_adjustment(
> (struct vega12_hwmgr *)(hwmgr->backend);
> struct PP_Clocks min_clocks = {0};
> struct pp_display_clock_request clock_req;
> - uint32_t clk_request;
>
> - if (hwmgr->display_config->num_display > 1)
> + if ((hwmgr->display_config->num_display > 1) &&
> + !hwmgr->display_config->multi_monitor_in_sync)
> vega12_notify_smc_display_change(hwmgr, false);
> else
> vega12_notify_smc_display_change(hwmgr, true);
> @@ -1426,15 +1426,6 @@ static int vega12_notify_smc_display_config_after_ps_adjustment(
> }
> }
>
> - if (data->smu_features[GNLD_DPM_UCLK].enabled) {
> - clk_request = (PPCLK_UCLK << 16) | (min_clocks.memoryClock) / 100;
> - PP_ASSERT_WITH_CODE(
> - smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_SetHardMinByFreq, clk_request) == 0,
> - "[PhwVega12_NotifySMCDisplayConfigAfterPowerStateAdjustment] Attempt to set UCLK HardMin Failed!",
> - return -1);
> - data->dpm_table.mem_table.dpm_state.hard_min_level = min_clocks.memoryClock;
> - }
> -
> return 0;
> }
>
> --
> 2.7.4
>
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