[PATCH 11/13] drm/amd/powerplay: set vega12 pre display configurations

[Alex Deucher]

On Tue, Jun 19, 2018 at 3:39 AM, Evan Quan <evan.quan at amd.com> wrote:
> PPSMC_MSG_NumOfDisplays is set as 0 and uclk is forced as
> highest.

Adjust the commit message to make it clear that you set num_displays
to 0 and force uclk high as part of the mode set dequence.

With that fixed:
Acked-by: Alex Deucher <alexander.deucher at amd.com>

>
> Change-Id: I2400279d3c979d99f4dd4b8d53f051cd8f8e0c33
> Signed-off-by: Evan Quan <evan.quan at amd.com>
> ---
>  drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c | 41 ++++++++++++++++++++++
>  1 file changed, 41 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
> index 26bdfff..1fadb71 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
> @@ -2110,6 +2110,45 @@ static int vega12_apply_clocks_adjust_rules(struct pp_hwmgr *hwmgr)
>         return 0;
>  }
>
> +static int vega12_set_uclk_to_highest_dpm_level(struct pp_hwmgr *hwmgr,
> +               struct vega12_single_dpm_table *dpm_table)
> +{
> +       struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
> +       int ret = 0;
> +
> +       if (data->smu_features[GNLD_DPM_UCLK].enabled) {
> +               PP_ASSERT_WITH_CODE(dpm_table->count > 0,
> +                               "[SetUclkToHightestDpmLevel] Dpm table has no entry!",
> +                               return -EINVAL);
> +               PP_ASSERT_WITH_CODE(dpm_table->count <= NUM_UCLK_DPM_LEVELS,
> +                               "[SetUclkToHightestDpmLevel] Dpm table has too many entries!",
> +                               return -EINVAL);
> +
> +               dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
> +               PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(hwmgr,
> +                               PPSMC_MSG_SetHardMinByFreq,
> +                               (PPCLK_UCLK << 16 ) | dpm_table->dpm_state.hard_min_level)),
> +                               "[SetUclkToHightestDpmLevel] Set hard min uclk failed!",
> +                               return ret);
> +       }
> +
> +       return ret;
> +}
> +
> +static int vega12_pre_display_configuration_changed_task(struct pp_hwmgr *hwmgr)
> +{
> +       struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
> +       int ret = 0;
> +
> +       smum_send_msg_to_smc_with_parameter(hwmgr,
> +                       PPSMC_MSG_NumOfDisplays, 0);
> +
> +       ret = vega12_set_uclk_to_highest_dpm_level(hwmgr,
> +                       &data->dpm_table.mem_table);
> +
> +       return ret;
> +}
> +
>  static int vega12_display_configuration_changed_task(struct pp_hwmgr *hwmgr)
>  {
>         struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
> @@ -2358,6 +2397,8 @@ static const struct pp_hwmgr_func vega12_hwmgr_funcs = {
>         .print_clock_levels = vega12_print_clock_levels,
>         .apply_clocks_adjust_rules =
>                 vega12_apply_clocks_adjust_rules,
> +       .pre_display_config_changed =
> +               vega12_pre_display_configuration_changed_task,
>         .display_config_changed = vega12_display_configuration_changed_task,
>         .powergate_uvd = vega12_power_gate_uvd,
>         .powergate_vce = vega12_power_gate_vce,
> --
> 2.7.4
>
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