[PATCH 2/5] drm/amd/pp: Fix wrong clock-unit exported to Display
Alex Deucher
alexdeucher at gmail.com
Wed Jun 20 03:47:27 UTC 2018
On Tue, Jun 19, 2018 at 5:17 PM, Harry Wentland <harry.wentland at amd.com> wrote:
> From: Rex Zhu <Rex.Zhu at amd.com>
>
> Transfer 10KHz (requested by smu) to KHz needed by Display
> component.
>
> This can fix the issue 4k Monitor can't be lit up on Vega/Raven.
>
> Signed-off-by: Rex Zhu <Rex.Zhu at amd.com>
> Acked-by: Alex Deucher <alexander.deucher at amd.com>
Need to make sure we drop Mikita's patch if we apply this one
otherwise the clocks will be wrong again.
Alex
> ---
> drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c | 4 ++--
> drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c | 10 +++++-----
> drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c | 10 +++++-----
> 3 files changed, 12 insertions(+), 12 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
> index d4bc83e81389..c905df42adc5 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
> @@ -993,7 +993,7 @@ static int smu10_get_clock_by_type_with_latency(struct pp_hwmgr *hwmgr,
>
> clocks->num_levels = 0;
> for (i = 0; i < pclk_vol_table->count; i++) {
> - clocks->data[i].clocks_in_khz = pclk_vol_table->entries[i].clk;
> + clocks->data[i].clocks_in_khz = pclk_vol_table->entries[i].clk * 10;
> clocks->data[i].latency_in_us = latency_required ?
> smu10_get_mem_latency(hwmgr,
> pclk_vol_table->entries[i].clk) :
> @@ -1044,7 +1044,7 @@ static int smu10_get_clock_by_type_with_voltage(struct pp_hwmgr *hwmgr,
>
> clocks->num_levels = 0;
> for (i = 0; i < pclk_vol_table->count; i++) {
> - clocks->data[i].clocks_in_khz = pclk_vol_table->entries[i].clk;
> + clocks->data[i].clocks_in_khz = pclk_vol_table->entries[i].clk * 10;
> clocks->data[i].voltage_in_mv = pclk_vol_table->entries[i].vol;
> clocks->num_levels++;
> }
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
> index 3b8d36df52e9..e9a8b527d481 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
> @@ -4067,7 +4067,7 @@ static void vega10_get_sclks(struct pp_hwmgr *hwmgr,
> for (i = 0; i < dep_table->count; i++) {
> if (dep_table->entries[i].clk) {
> clocks->data[clocks->num_levels].clocks_in_khz =
> - dep_table->entries[i].clk;
> + dep_table->entries[i].clk * 10;
> clocks->num_levels++;
> }
> }
> @@ -4104,7 +4104,7 @@ static void vega10_get_memclocks(struct pp_hwmgr *hwmgr,
> clocks->data[clocks->num_levels].clocks_in_khz =
> data->mclk_latency_table.entries
> [data->mclk_latency_table.count].frequency =
> - dep_table->entries[i].clk;
> + dep_table->entries[i].clk * 10;
> clocks->data[clocks->num_levels].latency_in_us =
> data->mclk_latency_table.entries
> [data->mclk_latency_table.count].latency =
> @@ -4126,7 +4126,7 @@ static void vega10_get_dcefclocks(struct pp_hwmgr *hwmgr,
> uint32_t i;
>
> for (i = 0; i < dep_table->count; i++) {
> - clocks->data[i].clocks_in_khz = dep_table->entries[i].clk;
> + clocks->data[i].clocks_in_khz = dep_table->entries[i].clk * 10;
> clocks->data[i].latency_in_us = 0;
> clocks->num_levels++;
> }
> @@ -4142,7 +4142,7 @@ static void vega10_get_socclocks(struct pp_hwmgr *hwmgr,
> uint32_t i;
>
> for (i = 0; i < dep_table->count; i++) {
> - clocks->data[i].clocks_in_khz = dep_table->entries[i].clk;
> + clocks->data[i].clocks_in_khz = dep_table->entries[i].clk * 10;
> clocks->data[i].latency_in_us = 0;
> clocks->num_levels++;
> }
> @@ -4202,7 +4202,7 @@ static int vega10_get_clock_by_type_with_voltage(struct pp_hwmgr *hwmgr,
> }
>
> for (i = 0; i < dep_table->count; i++) {
> - clocks->data[i].clocks_in_khz = dep_table->entries[i].clk;
> + clocks->data[i].clocks_in_khz = dep_table->entries[i].clk * 10;
> clocks->data[i].voltage_in_mv = (uint32_t)(table_info->vddc_lookup_table->
> entries[dep_table->entries[i].vddInd].us_vdd);
> clocks->num_levels++;
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
> index 782e2098824d..d685ce7f88cc 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
> @@ -1576,7 +1576,7 @@ static int vega12_get_sclks(struct pp_hwmgr *hwmgr,
>
> for (i = 0; i < ucount; i++) {
> clocks->data[i].clocks_in_khz =
> - dpm_table->dpm_levels[i].value * 100;
> + dpm_table->dpm_levels[i].value * 1000;
>
> clocks->data[i].latency_in_us = 0;
> }
> @@ -1608,7 +1608,7 @@ static int vega12_get_memclocks(struct pp_hwmgr *hwmgr,
>
> for (i = 0; i < ucount; i++) {
> clocks->data[i].clocks_in_khz =
> - dpm_table->dpm_levels[i].value * 100;
> + dpm_table->dpm_levels[i].value * 1000;
>
> clocks->data[i].latency_in_us =
> data->mclk_latency_table.entries[i].latency =
> @@ -1638,7 +1638,7 @@ static int vega12_get_dcefclocks(struct pp_hwmgr *hwmgr,
>
> for (i = 0; i < ucount; i++) {
> clocks->data[i].clocks_in_khz =
> - dpm_table->dpm_levels[i].value * 100;
> + dpm_table->dpm_levels[i].value * 1000;
>
> clocks->data[i].latency_in_us = 0;
> }
> @@ -1666,7 +1666,7 @@ static int vega12_get_socclocks(struct pp_hwmgr *hwmgr,
>
> for (i = 0; i < ucount; i++) {
> clocks->data[i].clocks_in_khz =
> - dpm_table->dpm_levels[i].value * 100;
> + dpm_table->dpm_levels[i].value * 1000;
>
> clocks->data[i].latency_in_us = 0;
> }
> @@ -1838,7 +1838,7 @@ static int vega12_print_clock_levels(struct pp_hwmgr *hwmgr,
> return -1);
> for (i = 0; i < clocks.num_levels; i++)
> size += sprintf(buf + size, "%d: %uMhz %s\n",
> - i, clocks.data[i].clocks_in_khz / 100,
> + i, clocks.data[i].clocks_in_khz / 1000,
> (clocks.data[i].clocks_in_khz == now) ? "*" : "");
> break;
>
> --
> 2.17.1
>
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