[PATCH] drm/amd/display: Fix a typo

[Alex Deucher]

On Wed, Jun 20, 2018 at 12:56 AM, Rex Zhu <Rex.Zhu at amd.com> wrote:
> change wm_min_memg_clk_in_khz -> wm_min_mem_clk_in_khz
>
> Signed-off-by: Rex Zhu <Rex.Zhu at amd.com>

Reviewed-by: Alex Deucher <alexander.deucher at amd.com>

> ---
>  drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c | 8 ++++----
>  drivers/gpu/drm/amd/display/dc/dm_services_types.h      | 6 +++---
>  2 files changed, 7 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c
> index 00c0a1e..943d74d 100644
> --- a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c
> +++ b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c
> @@ -1000,7 +1000,7 @@ static void bw_calcs_data_update_from_pplib(struct dc *dc)
>                         eng_clks.data[0].clocks_in_khz;
>         clk_ranges.wm_clk_ranges[0].wm_max_eng_clk_in_khz =
>                         eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz - 1;
> -       clk_ranges.wm_clk_ranges[0].wm_min_memg_clk_in_khz =
> +       clk_ranges.wm_clk_ranges[0].wm_min_mem_clk_in_khz =
>                         mem_clks.data[0].clocks_in_khz;
>         clk_ranges.wm_clk_ranges[0].wm_max_mem_clk_in_khz =
>                         mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz - 1;
> @@ -1010,7 +1010,7 @@ static void bw_calcs_data_update_from_pplib(struct dc *dc)
>                         eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz;
>         /* 5 GHz instead of data[7].clockInKHz to cover Overdrive */
>         clk_ranges.wm_clk_ranges[1].wm_max_eng_clk_in_khz = 5000000;
> -       clk_ranges.wm_clk_ranges[1].wm_min_memg_clk_in_khz =
> +       clk_ranges.wm_clk_ranges[1].wm_min_mem_clk_in_khz =
>                         mem_clks.data[0].clocks_in_khz;
>         clk_ranges.wm_clk_ranges[1].wm_max_mem_clk_in_khz =
>                         mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz - 1;
> @@ -1020,7 +1020,7 @@ static void bw_calcs_data_update_from_pplib(struct dc *dc)
>                         eng_clks.data[0].clocks_in_khz;
>         clk_ranges.wm_clk_ranges[2].wm_max_eng_clk_in_khz =
>                         eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz - 1;
> -       clk_ranges.wm_clk_ranges[2].wm_min_memg_clk_in_khz =
> +       clk_ranges.wm_clk_ranges[2].wm_min_mem_clk_in_khz =
>                         mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz;
>         /* 5 GHz instead of data[2].clockInKHz to cover Overdrive */
>         clk_ranges.wm_clk_ranges[2].wm_max_mem_clk_in_khz = 5000000;
> @@ -1030,7 +1030,7 @@ static void bw_calcs_data_update_from_pplib(struct dc *dc)
>                         eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz;
>         /* 5 GHz instead of data[7].clockInKHz to cover Overdrive */
>         clk_ranges.wm_clk_ranges[3].wm_max_eng_clk_in_khz = 5000000;
> -       clk_ranges.wm_clk_ranges[3].wm_min_memg_clk_in_khz =
> +       clk_ranges.wm_clk_ranges[3].wm_min_mem_clk_in_khz =
>                         mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz;
>         /* 5 GHz instead of data[2].clockInKHz to cover Overdrive */
>         clk_ranges.wm_clk_ranges[3].wm_max_mem_clk_in_khz = 5000000;
> diff --git a/drivers/gpu/drm/amd/display/dc/dm_services_types.h b/drivers/gpu/drm/amd/display/dc/dm_services_types.h
> index ab8c77d..2b83f92 100644
> --- a/drivers/gpu/drm/amd/display/dc/dm_services_types.h
> +++ b/drivers/gpu/drm/amd/display/dc/dm_services_types.h
> @@ -137,7 +137,7 @@ struct dm_pp_clock_range_for_wm_set {
>         enum dm_pp_wm_set_id wm_set_id;
>         uint32_t wm_min_eng_clk_in_khz;
>         uint32_t wm_max_eng_clk_in_khz;
> -       uint32_t wm_min_memg_clk_in_khz;
> +       uint32_t wm_min_mem_clk_in_khz;
>         uint32_t wm_max_mem_clk_in_khz;
>  };
>
> @@ -150,7 +150,7 @@ struct dm_pp_clock_range_for_dmif_wm_set_soc15 {
>         enum dm_pp_wm_set_id wm_set_id;
>         uint32_t wm_min_dcfclk_clk_in_khz;
>         uint32_t wm_max_dcfclk_clk_in_khz;
> -       uint32_t wm_min_memg_clk_in_khz;
> +       uint32_t wm_min_mem_clk_in_khz;
>         uint32_t wm_max_mem_clk_in_khz;
>  };
>
> @@ -158,7 +158,7 @@ struct dm_pp_clock_range_for_mcif_wm_set_soc15 {
>         enum dm_pp_wm_set_id wm_set_id;
>         uint32_t wm_min_socclk_clk_in_khz;
>         uint32_t wm_max_socclk_clk_in_khz;
> -       uint32_t wm_min_memg_clk_in_khz;
> +       uint32_t wm_min_mem_clk_in_khz;
>         uint32_t wm_max_mem_clk_in_khz;
>  };
>
> --
> 1.9.1
>
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