[PATCH 28/28] drm/amd/display: clean up dcn pplib notification call
Harry Wentland
harry.wentland at amd.com
Wed Mar 7 00:52:08 UTC 2018
From: Dmytro Laktyushkin <Dmytro.Laktyushkin at amd.com>
We have unused variables being populated when notifying pplib.
This change amends that.
Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin at amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng at amd.com>
Acked-by: Harry Wentland <harry.wentland at amd.com>
---
drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c | 4 +--
drivers/gpu/drm/amd/display/dc/core/dc_debug.c | 18 ++++-------
drivers/gpu/drm/amd/display/dc/dc.h | 4 +--
.../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 35 +++++-----------------
4 files changed, 15 insertions(+), 46 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
index 8bab3fec4d8d..4bb43a371292 100644
--- a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
+++ b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
@@ -983,8 +983,6 @@ bool dcn_validate_bandwidth(
context->bw.dcn.calc_clk.fclk_khz = (int)(bw_consumed * 1000000 / 32);
}
- context->bw.dcn.calc_clk.dram_ccm_us = (int)(v->dram_clock_change_margin);
- context->bw.dcn.calc_clk.min_active_dram_ccm_us = (int)(v->min_active_dram_clock_change_margin);
context->bw.dcn.calc_clk.dcfclk_deep_sleep_khz = (int)(v->dcf_clk_deep_sleep * 1000);
context->bw.dcn.calc_clk.dcfclk_khz = (int)(v->dcfclk * 1000);
@@ -998,7 +996,7 @@ bool dcn_validate_bandwidth(
dc->debug.min_disp_clk_khz;
}
- context->bw.dcn.calc_clk.max_dppclk_khz = context->bw.dcn.calc_clk.dispclk_khz / v->dispclk_dppclk_ratio;
+ context->bw.dcn.calc_clk.dppclk_khz = context->bw.dcn.calc_clk.dispclk_khz / v->dispclk_dppclk_ratio;
switch (v->voltage_level) {
case 0:
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_debug.c b/drivers/gpu/drm/amd/display/dc/core/dc_debug.c
index f82275eb81bc..5a552cb3f8a7 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_debug.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_debug.c
@@ -358,25 +358,19 @@ void context_clock_trace(
struct dal_logger *logger = core_dc->ctx->logger;
CLOCK_TRACE("Current: dispclk_khz:%d max_dppclk_khz:%d dcfclk_khz:%d\n"
- "dcfclk_deep_sleep_khz:%d fclk_khz:%d socclk_khz:%d\n"
- "dram_ccm_us:%d min_active_dram_ccm_us:%d\n",
+ "dcfclk_deep_sleep_khz:%d fclk_khz:%d socclk_khz:%d\n",
context->bw.dcn.calc_clk.dispclk_khz,
- context->bw.dcn.calc_clk.max_dppclk_khz,
+ context->bw.dcn.calc_clk.dppclk_khz,
context->bw.dcn.calc_clk.dcfclk_khz,
context->bw.dcn.calc_clk.dcfclk_deep_sleep_khz,
context->bw.dcn.calc_clk.fclk_khz,
- context->bw.dcn.calc_clk.socclk_khz,
- context->bw.dcn.calc_clk.dram_ccm_us,
- context->bw.dcn.calc_clk.min_active_dram_ccm_us);
+ context->bw.dcn.calc_clk.socclk_khz);
CLOCK_TRACE("Calculated: dispclk_khz:%d max_dppclk_khz:%d dcfclk_khz:%d\n"
- "dcfclk_deep_sleep_khz:%d fclk_khz:%d socclk_khz:%d\n"
- "dram_ccm_us:%d min_active_dram_ccm_us:%d\n",
+ "dcfclk_deep_sleep_khz:%d fclk_khz:%d socclk_khz:%d\n",
context->bw.dcn.calc_clk.dispclk_khz,
- context->bw.dcn.calc_clk.max_dppclk_khz,
+ context->bw.dcn.calc_clk.dppclk_khz,
context->bw.dcn.calc_clk.dcfclk_khz,
context->bw.dcn.calc_clk.dcfclk_deep_sleep_khz,
- context->bw.dcn.calc_clk.fclk_khz,
- context->bw.dcn.calc_clk.dram_ccm_us,
- context->bw.dcn.calc_clk.min_active_dram_ccm_us);
+ context->bw.dcn.calc_clk.fclk_khz);
#endif
}
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
index 1a7e7a645a6e..fa4b3c8b3bb7 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -186,14 +186,12 @@ enum wm_report_mode {
struct dc_clocks {
int dispclk_khz;
- int max_dppclk_khz;
int max_supported_dppclk_khz;
+ int dppclk_khz;
int dcfclk_khz;
int socclk_khz;
int dcfclk_deep_sleep_khz;
int fclk_khz;
- int dram_ccm_us;
- int min_active_dram_ccm_us;
};
struct dc_debug {
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index 9f9b910b7f6d..4365906b14ee 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -1703,7 +1703,7 @@ static void update_dchubp_dpp(
* divided by 2
*/
if (plane_state->update_flags.bits.full_update) {
- bool should_divided_by_2 = context->bw.dcn.calc_clk.max_dppclk_khz <=
+ bool should_divided_by_2 = context->bw.dcn.calc_clk.dppclk_khz <=
context->bw.dcn.cur_clk.dispclk_khz / 2;
dpp->funcs->dpp_dppclk_control(
@@ -1711,7 +1711,7 @@ static void update_dchubp_dpp(
should_divided_by_2,
true);
- dc->current_state->bw.dcn.cur_clk.max_dppclk_khz =
+ dc->current_state->bw.dcn.cur_clk.dppclk_khz =
should_divided_by_2 ?
context->bw.dcn.cur_clk.dispclk_khz / 2 :
context->bw.dcn.cur_clk.dispclk_khz;
@@ -1904,16 +1904,10 @@ static void dcn10_pplib_apply_display_requirements(
{
struct dm_pp_display_configuration *pp_display_cfg = &context->pp_display_cfg;
- pp_display_cfg->all_displays_in_sync = false;/*todo*/
- pp_display_cfg->nb_pstate_switch_disable = false;
pp_display_cfg->min_engine_clock_khz = context->bw.dcn.cur_clk.dcfclk_khz;
pp_display_cfg->min_memory_clock_khz = context->bw.dcn.cur_clk.fclk_khz;
pp_display_cfg->min_engine_clock_deep_sleep_khz = context->bw.dcn.cur_clk.dcfclk_deep_sleep_khz;
pp_display_cfg->min_dcfc_deep_sleep_clock_khz = context->bw.dcn.cur_clk.dcfclk_deep_sleep_khz;
- pp_display_cfg->avail_mclk_switch_time_us =
- context->bw.dcn.cur_clk.dram_ccm_us > 0 ? context->bw.dcn.cur_clk.dram_ccm_us : 0;
- pp_display_cfg->avail_mclk_switch_time_in_disp_active_us =
- context->bw.dcn.cur_clk.min_active_dram_ccm_us > 0 ? context->bw.dcn.cur_clk.min_active_dram_ccm_us : 0;
pp_display_cfg->min_dcfclock_khz = context->bw.dcn.cur_clk.dcfclk_khz;
pp_display_cfg->disp_clk_khz = context->bw.dcn.cur_clk.dispclk_khz;
dce110_fill_display_configs(context, pp_display_cfg);
@@ -2126,12 +2120,12 @@ static inline bool should_set_clock(bool decrease_allowed, int calc_clk, int cur
static int determine_dppclk_threshold(struct dc *dc, struct dc_state *context)
{
bool request_dpp_div = context->bw.dcn.calc_clk.dispclk_khz >
- context->bw.dcn.calc_clk.max_dppclk_khz;
+ context->bw.dcn.calc_clk.dppclk_khz;
bool dispclk_increase = context->bw.dcn.calc_clk.dispclk_khz >
context->bw.dcn.cur_clk.dispclk_khz;
int disp_clk_threshold = context->bw.dcn.calc_clk.max_supported_dppclk_khz;
bool cur_dpp_div = context->bw.dcn.cur_clk.dispclk_khz >
- context->bw.dcn.cur_clk.max_dppclk_khz;
+ context->bw.dcn.cur_clk.dppclk_khz;
/* increase clock, looking for div is 0 for current, request div is 1*/
if (dispclk_increase) {
@@ -2176,7 +2170,7 @@ static void ramp_up_dispclk_with_dpp(struct dc *dc, struct dc_state *context)
{
int i;
bool request_dpp_div = context->bw.dcn.calc_clk.dispclk_khz >
- context->bw.dcn.calc_clk.max_dppclk_khz;
+ context->bw.dcn.calc_clk.dppclk_khz;
int dispclk_to_dpp_threshold = determine_dppclk_threshold(dc, context);
@@ -2207,8 +2201,8 @@ static void ramp_up_dispclk_with_dpp(struct dc *dc, struct dc_state *context)
context->bw.dcn.cur_clk.dispclk_khz =
context->bw.dcn.calc_clk.dispclk_khz;
- context->bw.dcn.cur_clk.max_dppclk_khz =
- context->bw.dcn.calc_clk.max_dppclk_khz;
+ context->bw.dcn.cur_clk.dppclk_khz =
+ context->bw.dcn.calc_clk.dppclk_khz;
context->bw.dcn.cur_clk.max_supported_dppclk_khz =
context->bw.dcn.calc_clk.max_supported_dppclk_khz;
}
@@ -2275,21 +2269,6 @@ static void dcn10_set_bandwidth(
ramp_up_dispclk_with_dpp(dc, context);
}
- /* Decrease in freq is increase in period so opposite comparison for dram_ccm */
- if ((decrease_allowed && context->bw.dcn.calc_clk.dram_ccm_us
- > dc->current_state->bw.dcn.cur_clk.dram_ccm_us) ||
- context->bw.dcn.calc_clk.dram_ccm_us
- < dc->current_state->bw.dcn.cur_clk.dram_ccm_us) {
- context->bw.dcn.cur_clk.dram_ccm_us =
- context->bw.dcn.calc_clk.dram_ccm_us;
- }
- if ((decrease_allowed && context->bw.dcn.calc_clk.min_active_dram_ccm_us
- > dc->current_state->bw.dcn.cur_clk.min_active_dram_ccm_us) ||
- context->bw.dcn.calc_clk.min_active_dram_ccm_us
- < dc->current_state->bw.dcn.cur_clk.min_active_dram_ccm_us) {
- context->bw.dcn.cur_clk.min_active_dram_ccm_us =
- context->bw.dcn.calc_clk.min_active_dram_ccm_us;
- }
dcn10_pplib_apply_display_requirements(dc, context);
if (dc->debug.sanity_checks) {
--
2.14.1
More information about the amd-gfx
mailing list