[PATCH v2] drm/amdgpu: Clean sdma wptr register when only enable wptr polling

[Christian König]

Reviewed-by: Christian König <christian.koenig at amd.com>.

Am 07.03.2018 um 07:17 schrieb Yu, Xiangliang:
> Reviewed-by: Xiangliang Yu <Xiangliang.Yu at amd.com>
>
>
>> -----Original Message-----
>> From: amd-gfx [mailto:amd-gfx-bounces at lists.freedesktop.org] On Behalf
>> Of Emily Deng
>> Sent: Wednesday, March 07, 2018 9:52 AM
>> To: amd-gfx at lists.freedesktop.org
>> Cc: Deng, Emily <Emily.Deng at amd.com>
>> Subject: [PATCH v2] drm/amdgpu: Clean sdma wptr register when only
>> enable wptr polling
>>
>> The sdma wptr polling memory is not fast enough, then the sdma wptr
>> register will be random, and not equal to sdma rptr, which will cause sdma
>> engine hang when load driver, so clean up the sdma wptr directly to fix this
>> issue.
>>
>> v2:add comment above the code and correct coding style
>> Signed-off-by: Emily Deng <Emily.Deng at amd.com>
>> ---
>>   drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c | 7 +++++--
>>   1 file changed, 5 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
>> b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
>> index 521978c..89ec17c 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
>> @@ -719,14 +719,17 @@ static int sdma_v3_0_gfx_resume(struct
>> amdgpu_device *adev)
>>   		WREG32(mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI +
>> sdma_offsets[i],
>>   		       upper_32_bits(wptr_gpu_addr));
>>   		wptr_poll_cntl =
>> RREG32(mmSDMA0_GFX_RB_WPTR_POLL_CNTL + sdma_offsets[i]);
>> -		if (ring->use_pollmem)
>> +		if (ring->use_pollmem) {
>> +			/*wptr polling is not enogh fast, directly clean the
>> wptr register */
>> +			WREG32(mmSDMA0_GFX_RB_WPTR +
>> sdma_offsets[i], 0);
>>   			wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl,
>>
>> SDMA0_GFX_RB_WPTR_POLL_CNTL,
>>   						       ENABLE, 1);
>> -		else
>> +		} else {
>>   			wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl,
>>
>> SDMA0_GFX_RB_WPTR_POLL_CNTL,
>>   						       ENABLE, 0);
>> +		}
>>   		WREG32(mmSDMA0_GFX_RB_WPTR_POLL_CNTL +
>> sdma_offsets[i], wptr_poll_cntl);
>>
>>   		/* enable DMA RB */
>> --
>> 2.7.4
>>
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