vga handover for raven

Tom St Denis tstdenis at amd.com
Wed Mar 14 13:54:40 UTC 2018


Hi,

In the original version of the patch we had:

@@ -358,7 +360,9 @@ struct dce_hwseq_registers { 
 

         HWSEQ_PIXEL_RATE_MASK_SH_LIST(mask_sh, OTG0_),\
         HWS_SF1(OTG0_, PHYPLL_PIXEL_RATE_CNTL, 
PHYPLL_PIXEL_RATE_SOURCE, mask_sh), \
         HWS_SF(, DCHUBBUB_GLOBAL_TIMER_CNTL, 
DCHUBBUB_GLOBAL_TIMER_ENABLE, mask_sh), \
-       HWS_SF(, DCFCLK_CNTL, DCFCLK_GATE_DIS, mask_sh) 
 

+       HWS_SF(, DCFCLK_CNTL, DCFCLK_GATE_DIS, mask_sh),\ 
 

+       HWS_SF(, VGA_TEST_CONTROL, VGA_TEST_ENABLE, mask_sh),\ 
 

+       HWS_SF(, VGA_TEST_CONTROL, VGA_TEST_RENDER_START, mask_sh) 
 



Which somehow changed into

@@ -404,7 +406,9 @@ struct dce_hwseq_registers { 

         HWS_SF(, DOMAIN7_PG_STATUS, DOMAIN7_PGFSM_PWR_STATUS, mask_sh), \
         HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh), \
         HWS_SF(, LVTMA_PWRSEQ_CNTL, LVTMA_BLON, mask_sh), \
-       HWS_SF(, LVTMA_PWRSEQ_STATE, LVTMA_PWRSEQ_TARGET_STATE_R, 
mask_sh)
+       HWS_SF(, LVTMA_PWRSEQ_STATE, LVTMA_PWRSEQ_TARGET_STATE_R, 
mask_sh), \
+       HWS_SF(, VGA_TEST_CONTROL, VGA_TEST_ENABLE, mask_sh),\ 

+       HWS_SF(, VGA_TEST_CONTROL, VGA_TEST_RENDER_START, mask_sh) 


And the net result is the display doesn't work (same glitches as before) 
on a raven1 device.

Tom


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