[PATCH] drm/amd/display: Refine disable VGA

[Alex Deucher]

On Thu, Mar 15, 2018 at 11:07 AM, Harry Wentland <harry.wentland at amd.com> wrote:
> From: Clark Zheng <clark.zheng at amd.com>
>
> bad case won't follow normal sense, it will not enable vga1 as usual, but vga2,3,4 is on.
>
> Signed-off-by: Clark Zheng <clark.zheng at amd.com>
> Reviewed-by: Tony Cheng <tony.cheng at amd.com>

Acked-by: Alex Deucher <alexander.deucher at amd.com>

> ---
>  drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h       |  8 +++++++-
>  .../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c    | 20 +++++++++++++++-----
>  2 files changed, 22 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h
> index 18dbd0bd7874..057b8afd74bc 100644
> --- a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h
> +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h
> @@ -408,6 +408,9 @@ struct dce_hwseq_registers {
>         HWS_SF(, DOMAIN7_PG_STATUS, DOMAIN7_PGFSM_PWR_STATUS, mask_sh), \
>         HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh), \
>         HWS_SF(, D1VGA_CONTROL, D1VGA_MODE_ENABLE, mask_sh),\
> +       HWS_SF(, D2VGA_CONTROL, D2VGA_MODE_ENABLE, mask_sh),\
> +       HWS_SF(, D3VGA_CONTROL, D3VGA_MODE_ENABLE, mask_sh),\
> +       HWS_SF(, D4VGA_CONTROL, D4VGA_MODE_ENABLE, mask_sh),\
>         HWS_SF(, VGA_TEST_CONTROL, VGA_TEST_ENABLE, mask_sh),\
>         HWS_SF(, VGA_TEST_CONTROL, VGA_TEST_RENDER_START, mask_sh),\
>         HWS_SF(, LVTMA_PWRSEQ_CNTL, LVTMA_BLON, mask_sh), \
> @@ -497,7 +500,10 @@ struct dce_hwseq_registers {
>         type DENTIST_DISPCLK_WDIVIDER; \
>         type VGA_TEST_ENABLE; \
>         type VGA_TEST_RENDER_START; \
> -       type D1VGA_MODE_ENABLE;
> +       type D1VGA_MODE_ENABLE; \
> +       type D2VGA_MODE_ENABLE; \
> +       type D3VGA_MODE_ENABLE; \
> +       type D4VGA_MODE_ENABLE;
>
>  struct dce_hwseq_shift {
>         HWSEQ_REG_FIELD_LIST(uint8_t)
> diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
> index 4365906b14ee..8b0f6b8a5627 100644
> --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
> +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
> @@ -220,14 +220,24 @@ static void enable_power_gating_plane(
>  static void disable_vga(
>         struct dce_hwseq *hws)
>  {
> -       unsigned int in_vga_mode = 0;
> -
> -       REG_GET(D1VGA_CONTROL, D1VGA_MODE_ENABLE, &in_vga_mode);
> -
> -       if (in_vga_mode == 0)
> +       unsigned int in_vga1_mode = 0;
> +       unsigned int in_vga2_mode = 0;
> +       unsigned int in_vga3_mode = 0;
> +       unsigned int in_vga4_mode = 0;
> +
> +       REG_GET(D1VGA_CONTROL, D1VGA_MODE_ENABLE, &in_vga1_mode);
> +       REG_GET(D2VGA_CONTROL, D2VGA_MODE_ENABLE, &in_vga2_mode);
> +       REG_GET(D3VGA_CONTROL, D3VGA_MODE_ENABLE, &in_vga3_mode);
> +       REG_GET(D4VGA_CONTROL, D4VGA_MODE_ENABLE, &in_vga4_mode);
> +
> +       if (in_vga1_mode == 0 && in_vga2_mode == 0 &&
> +                       in_vga3_mode == 0 && in_vga4_mode == 0)
>                 return;
>
>         REG_WRITE(D1VGA_CONTROL, 0);
> +       REG_WRITE(D2VGA_CONTROL, 0);
> +       REG_WRITE(D3VGA_CONTROL, 0);
> +       REG_WRITE(D4VGA_CONTROL, 0);
>
>         /* HW Engineer's Notes:
>          *  During switch from vga->extended, if we set the VGA_TEST_ENABLE and
> --
> 2.14.1
>
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