[PATCH 00/57] Vega20 support
Christian König
ckoenig.leichtzumerken at gmail.com
Wed May 16 07:40:56 UTC 2018
Patches #1, #15, #18, #30, #33-#36, #39, #53-#54, #56 are Acked-by:
Christian König <christian.koenig at amd.com>.
Patches #2-#14, #16-#17, #20-#25, #28, #31, #40, #43, #55, #57 are
Reviewed-by: Christian König <christian.koenig at amd.com>.
Patch #19 still has a "//TODO: Need to update this for vega20" comment
in the middle of the code.
Should probably either be removed or fixed.
Patch #26:
> if (adev->flags & AMD_IS_APU)
> adev->nbio_funcs = &nbio_v7_0_funcs;
> + else if (adev->asic_type == CHIP_VEGA20)
> + adev->nbio_funcs = &nbio_v7_0_funcs;
Wouldn't it be better to write that as "adev->asic_type >= CHIP_VEGA20" now?
Patch #27: How about we push all those magic register values for
emulation into firmware files?
Nobody outside of AMD is ever going to use this or be able to test it.
Patch #29: Looks like spaces instead of tabs for indentation.
Patch #32:
> +#ifndef CONFIG_DRM_AMD_DC_VG20
> dce_clk_params.flags.USE_GENLOCK_AS_SOURCE_FOR_DPREFCLK =
> (dce_clk_params.pll_id ==
> CLOCK_SOURCE_COMBO_DISPLAY_PLL0);
> +#else
> + if (!ASICREV_IS_VEGA20_P(clk->ctx->asic_id.hw_internal_rev))
> + dce_clk_params.flags.USE_GENLOCK_AS_SOURCE_FOR_DPREFCLK =
> + (dce_clk_params.pll_id ==
> + CLOCK_SOURCE_COMBO_DISPLAY_PLL0);
> + else
> + dce_clk_params.flags.USE_GENLOCK_AS_SOURCE_FOR_DPREFCLK = false;
> +#endif
That should certainly be cleaned up, looks like we can just keep the
"#else" part.
Patch #37: Why not the other way around?
Patch #38: Well that explains patch #37 :) Should probably be squashed
into the previous patches.
Patch #41: Should be squashed into the original patch adding the file.
Patch #42: That looks odd, what is the background?
Patches #44 - #52: Need to take a closer look later on.
Cheers,
Christian.
Am 15.05.2018 um 16:58 schrieb Alex Deucher:
> This patch set adds initial support for vega20.
>
> Alex Deucher (6):
> drm/amdgpu/atomfirmware: add new gfx_info data table v2.4 (v2)
> drm/amdgpu/atomfirmware: add parser for gfx_info table
> drm/amdgpu/vg20: fallback to vbios table if gpu info fw is not
> available (v2)
> drm/amdgpu: drop gpu_info firmware for vega20
> drm/amdgpu: add df 3.6 headers
> drm/amdgpu: flag Vega20 as experimental
>
> Evan Quan (1):
> drm/amd/powerplay: update vega20 cg flags
>
> Feifei Xu (35):
> drm/amd: Add vega20_ip_offset.h headerfile for vega20.
> drm/amdgpu: Add vega20 to asic_type enum.
> drm/amdgpu: Add gpu_info firmware for vega20.
> drm/amdgpu: set asic family for vega20.
> drm/amdgpu: Add smu firmware support for vega20
> drm/amdgpu/powerplay: Add initial vega20 support v2
> drm/amdgpu/psp: Add initial psp support for vega20
> drm/amdgpu: Add vega20 ucode loading method
> drm/amdgpu: Specify vega20 uvd firmware
> drm/amdgpu: Specify vega20 vce firmware
> drm/amdgpu/virtual_dce: Add vega20 support
> drm/amdgpu/gmc9: Add vega20 support
> drm/amdgpu/mmhub: Add clockgating support for vega20
> drm/amdgpu/sdma4: Specify vega20 firmware
> drm/amdgpu/sdma4: Add vega20 golden settings (v3)
> drm/amdgpu/sdma4: Add clockgating support for vega20
> drm/amdgpu/gfx9: Add support for vega20 firmware
> drm/amdgpu/gfx9: Add vega20 golden settings (v3)
> drm/amdgpu/gfx9: Add gfx config for vega20. (v3)
> drm/amdgpu/gfx9: Add support for vega20
> drm/amdgpu/gfx9: Add clockgatting support for vega20
> drm/amdgpu/soc15:Add vega20 soc15_common_early_init support
> drm/amdgpu/soc15: Set common clockgating for vega20.
> drm/amdgpu/soc15: dynamic initialize ip offset for vega20
> drm/amdgpu/soc15: Add ip blocks for vega20 (v2)
> drm/amdgpu: Add nbio support for vega20 (v2)
> drm/amd/display/dm: Add vega20 support
> drm/amdgpu: Add vega20 to dc support check
> drm/amd/display: Remove COMBO_DISPLAY_PLL0 from Vega20
> drm/amdgpu: Set vega20 load_type to AMDGPU_FW_LOAD_DIRECT.
> drm/include: Fix MP1_BASE address for vega20
> drm/amdgpu: Disable ip modules that are not ready yet
> drm/amdgpu/df: implement df v3_6 callback functions (v2)
> drm/amdgpu: Switch to use df_v3_6_funcs for vega20 (v2)
> drm/amdgpu: Add vega20 pci ids
>
> James Zhu (10):
> drm/amd/include/vg20: adjust VCE_BASE to reuse vce 4.0 header files
> drm/amdgpu/vg20:Restruct uvd to support multiple uvds
> drm/amdgpu/vg20:Restruct uvd.inst to support multiple instances
> drm/amdgpu/vg20:Restruct uvd.idle_work to support multiple instance
> (v2)
> drm/amdgpu/vg20:increase 3 rings for AMDGPU_MAX_RINGS
> drm/amdgpu/vg20:Enable the 2nd instance for uvd
> drm/amdgpu/vg20:Add IH client ID for the 2nd UVD
> drm/amdgpu/vg20:Enable the 2nd instance IRQ for uvd 7.2
> drm/amdgpu/vg20:Enable 2nd instance queue maping for uvd 7.2
> drm/amdgpu/vg20:Enable UVD/VCE for Vega20
>
> Jerry (Fangzhi) Zuo (3):
> drm/amd/display: Add Vega20 config. support
> drm/amd/display: Add BIOS smu_info v3_3 support for Vega20
> drm/amd/display: Add harvest IP support for Vega20
>
> Roman Li (1):
> drm/amd: Add dce-12.1 gpio aux registers
>
> Shaoyun Liu (1):
> drm/amdgpu: Add vega20 soc init sequence on emulator (v3)
>
> drivers/gpu/drm/amd/amdgpu/Makefile | 6 +-
> drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c | 46 +
> drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.h | 1 +
> drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c | 3 +
> drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 4 +
> drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 7 +
> drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c | 6 +-
> drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 12 +-
> drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 1 +
> drivers/gpu/drm/amd/amdgpu/amdgpu_queue_mgr.c | 14 +-
> drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c | 1 +
> drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h | 2 +-
> drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c | 2 +
> drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c | 283 +-
> drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.h | 26 +-
> drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c | 5 +
> drivers/gpu/drm/amd/amdgpu/dce_virtual.c | 1 +
> drivers/gpu/drm/amd/amdgpu/df_v3_6.c | 116 +
> drivers/gpu/drm/amd/amdgpu/df_v3_6.h | 40 +
> drivers/gpu/drm/amd/amdgpu/emu_soc.c | 10091 +++++++++++++++++++
> drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 60 +-
> drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 3 +
> drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c | 1 +
> drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c | 18 +-
> drivers/gpu/drm/amd/amdgpu/psp_v3_1.c | 3 +
> drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 33 +
> drivers/gpu/drm/amd/amdgpu/soc15.c | 43 +-
> drivers/gpu/drm/amd/amdgpu/soc15.h | 1 +
> drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c | 27 +-
> drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c | 25 +-
> drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c | 77 +-
> drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c | 1050 +-
> drivers/gpu/drm/amd/amdgpu/vega20_reg_init.c | 53 +
> drivers/gpu/drm/amd/display/Kconfig | 9 +
> drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 4 +
> drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c | 5 +
> drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c | 11 +-
> .../drm/amd/display/dc/dce120/dce120_resource.c | 208 +
> drivers/gpu/drm/amd/display/include/dal_asic_id.h | 6 +
> .../drm/amd/include/asic_reg/dce/dce_12_0_offset.h | 12 +
> .../amd/include/asic_reg/dce/dce_12_0_sh_mask.h | 152 +
> .../drm/amd/include/asic_reg/df/df_3_6_default.h | 26 +
> .../drm/amd/include/asic_reg/df/df_3_6_offset.h | 33 +
> .../drm/amd/include/asic_reg/df/df_3_6_sh_mask.h | 48 +
> drivers/gpu/drm/amd/include/atomfirmware.h | 34 +
> drivers/gpu/drm/amd/include/soc15_ih_clientid.h | 1 +
> drivers/gpu/drm/amd/include/vega20_ip_offset.h | 1051 ++
> drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c | 1 +
> drivers/gpu/drm/amd/powerplay/smumgr/smumgr.c | 1 +
> include/drm/amd_asic_type.h | 1 +
> 50 files changed, 12949 insertions(+), 715 deletions(-)
> create mode 100644 drivers/gpu/drm/amd/amdgpu/df_v3_6.c
> create mode 100644 drivers/gpu/drm/amd/amdgpu/df_v3_6.h
> create mode 100644 drivers/gpu/drm/amd/amdgpu/vega20_reg_init.c
> mode change 100644 => 100755 drivers/gpu/drm/amd/include/asic_reg/dce/dce_12_0_offset.h
> mode change 100644 => 100755 drivers/gpu/drm/amd/include/asic_reg/dce/dce_12_0_sh_mask.h
> create mode 100644 drivers/gpu/drm/amd/include/asic_reg/df/df_3_6_default.h
> create mode 100644 drivers/gpu/drm/amd/include/asic_reg/df/df_3_6_offset.h
> create mode 100644 drivers/gpu/drm/amd/include/asic_reg/df/df_3_6_sh_mask.h
> create mode 100644 drivers/gpu/drm/amd/include/vega20_ip_offset.h
>
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