[PATCH 2/6] drm/amd/pp: Add smu support for vcn cg/pg on RV

[Alex Deucher]

On Wed, May 16, 2018 at 8:52 AM, Rex Zhu <Rex.Zhu at amd.com> wrote:
> Signed-off-by: Rex Zhu <Rex.Zhu at amd.com>

Reviewed-by: Alex Deucher <alexander.deucher at amd.com>

> ---
>  drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c | 25 ++++++++++++++++++++++-
>  1 file changed, 24 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
> index 32b1524..436326b 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
> @@ -1146,6 +1146,29 @@ static int smu10_set_mmhub_powergating_by_smu(struct pp_hwmgr *hwmgr)
>         return smum_send_msg_to_smc(hwmgr, PPSMC_MSG_PowerGateMmHub);
>  }
>
> +static void smu10_powergate_vcn(struct pp_hwmgr *hwmgr, bool bgate)
> +{
> +       if (bgate) {
> +               amdgpu_device_ip_set_powergating_state(hwmgr->adev,
> +                                               AMD_IP_BLOCK_TYPE_VCN,
> +                                               AMD_PG_STATE_GATE);
> +               amdgpu_device_ip_set_clockgating_state(hwmgr->adev,
> +                                               AMD_IP_BLOCK_TYPE_VCN,
> +                                               AMD_CG_STATE_GATE);
> +               smum_send_msg_to_smc_with_parameter(hwmgr,
> +                                       PPSMC_MSG_PowerDownVcn, 0);
> +       } else {
> +               smum_send_msg_to_smc_with_parameter(hwmgr,
> +                                               PPSMC_MSG_PowerUpVcn, 0);
> +               amdgpu_device_ip_set_clockgating_state(hwmgr->adev,
> +                                               AMD_IP_BLOCK_TYPE_VCN,
> +                                               AMD_CG_STATE_UNGATE);
> +               amdgpu_device_ip_set_powergating_state(hwmgr->adev,
> +                                               AMD_IP_BLOCK_TYPE_VCN,
> +                                               AMD_PG_STATE_UNGATE);
> +       }
> +}
> +
>  static const struct pp_hwmgr_func smu10_hwmgr_funcs = {
>         .backend_init = smu10_hwmgr_backend_init,
>         .backend_fini = smu10_hwmgr_backend_fini,
> @@ -1154,7 +1177,7 @@ static int smu10_set_mmhub_powergating_by_smu(struct pp_hwmgr *hwmgr)
>         .force_dpm_level = smu10_dpm_force_dpm_level,
>         .get_power_state_size = smu10_get_power_state_size,
>         .powerdown_uvd = NULL,
> -       .powergate_uvd = NULL,
> +       .powergate_uvd = smu10_powergate_vcn,
>         .powergate_vce = NULL,
>         .get_mclk = smu10_dpm_get_mclk,
>         .get_sclk = smu10_dpm_get_sclk,
> --
> 1.9.1
>
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