[PATCH 1/4] drm/amdgpu: add new DF 1.7 register defs

[Zhang, Hawking]

Series is Reviewed-by: Hawking Zhang <Hawking.Zhang at amd.com>

Regards,
Hawking

-----Original Message-----
From: amd-gfx <amd-gfx-bounces at lists.freedesktop.org> On Behalf Of Alex Deucher
Sent: 2018年5月19日 3:48
To: amd-gfx list <amd-gfx at lists.freedesktop.org>
Cc: Deucher, Alexander <Alexander.Deucher at amd.com>
Subject: Re: [PATCH 1/4] drm/amdgpu: add new DF 1.7 register defs

Ping?

On Wed, May 16, 2018 at 4:51 PM, Alex Deucher <alexdeucher at gmail.com> wrote:
> Signed-off-by: Alex Deucher <alexander.deucher at amd.com>
> ---
>  drivers/gpu/drm/amd/include/asic_reg/df/df_1_7_offset.h  | 4 ++++  
> drivers/gpu/drm/amd/include/asic_reg/df/df_1_7_sh_mask.h | 4 ++++
>  2 files changed, 8 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/include/asic_reg/df/df_1_7_offset.h 
> b/drivers/gpu/drm/amd/include/asic_reg/df/df_1_7_offset.h
> index 2b305dd021e8..e6044e27a913 100644
> --- a/drivers/gpu/drm/amd/include/asic_reg/df/df_1_7_offset.h
> +++ b/drivers/gpu/drm/amd/include/asic_reg/df/df_1_7_offset.h
> @@ -30,4 +30,8 @@
>  #define mmDF_CS_AON0_DramBaseAddress0                                                                  0x0044
>  #define mmDF_CS_AON0_DramBaseAddress0_BASE_IDX                                                         0
>
> +#define mmDF_CS_AON0_CoherentSlaveModeCtrlA0                                                           0x0214
> +#define mmDF_CS_AON0_CoherentSlaveModeCtrlA0_BASE_IDX                                                  0
> +
> +
>  #endif
> diff --git a/drivers/gpu/drm/amd/include/asic_reg/df/df_1_7_sh_mask.h 
> b/drivers/gpu/drm/amd/include/asic_reg/df/df_1_7_sh_mask.h
> index 2ba849798924..a78c99480e2d 100644
> --- a/drivers/gpu/drm/amd/include/asic_reg/df/df_1_7_sh_mask.h
> +++ b/drivers/gpu/drm/amd/include/asic_reg/df/df_1_7_sh_mask.h
> @@ -45,4 +45,8 @@
>  #define DF_CS_AON0_DramBaseAddress0__IntLvAddrSel_MASK                                                 0x00000700L
>  #define DF_CS_AON0_DramBaseAddress0__DramBaseAddr_MASK                                                 0xFFFFF000L
>
> +//DF_CS_AON0_CoherentSlaveModeCtrlA0
> +#define DF_CS_AON0_CoherentSlaveModeCtrlA0__ForceParWrRMW__SHIFT                                       0x3
> +#define DF_CS_AON0_CoherentSlaveModeCtrlA0__ForceParWrRMW_MASK                                         0x00000008L
> +
>  #endif
> --
> 2.13.6
>
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