[PATCH 10/17] drm/amdgpu: add patch for fixing a known bug

[Christian König]

Am 24.05.2018 um 22:15 schrieb boyuan.zhang at amd.com:
> From: Boyuan Zhang <boyuan.zhang at amd.com>
>
> Allocate extra space in vcn jpeg ring buffer and store the jpeg ring patch
>
> Signed-off-by: Boyuan Zhang <boyuan.zhang at amd.com>
> ---
>   drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 27 ++++++++++++++++++++++++++-
>   1 file changed, 26 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
> index dcd1a9a..2e4bd26 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
> @@ -119,7 +119,8 @@ static int vcn_v1_0_sw_init(void *handle)
>   
>   	ring = &adev->vcn.ring_jpeg;
>   	sprintf(ring->name, "vcn_jpeg");
> -	r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.irq, 0);
> +	/* allocate extra dw in ring buffer for storing patch commands */
> +	r = amdgpu_ring_init(adev, ring, 512 + 64, &adev->vcn.irq, 0);
>   	if (r)
>   		return r;
>   
> @@ -679,6 +680,30 @@ static int vcn_v1_0_start(struct amdgpu_device *adev)
>   	WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_WPTR, 0);
>   	WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_CNTL, 0x00000002L);
>   
> +	/* set wptr to the extra allocated space in ring buffer */
> +	ring->wptr = RREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_WPTR);
> +	ring->wptr += ring->max_dw * amdgpu_sched_hw_submission;
> +
> +	/* increase mask to allow to write to the extra space */
> +	ring->buf_mask += 64 * 4;
> +	ring->ptr_mask += 64 * 4;

Well that is rather ugly. buf_mask and ptr_mask are bit masks, you could 
set them to 0xffffffff but what you do here might not work as expected.

> +
> +	/* allocate extra space */
> +	r = amdgpu_ring_alloc(ring, 64);
> +	if (r) {
> +		DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n",
> +				  ring->idx, r);
> +		return r;
> +	}
> +
> +	/* copy patch commands to the extra space */
> +	vcn_v1_0_jpeg_ring_set_patch_ring(ring);

Can't vcn_v1_0_jpeg_ring_set_patch_ring() just patch the command 
directly to he end of the ring buffer?

In other words why do we need to use amdgpu_ring_write() in 
vcn_v1_0_jpeg_ring_set_patch_ring()?

Christian.

> +
> +	/* reset wptr and mask */
> +	ring->wptr = RREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_WPTR);
> +	ring->buf_mask -= 0x100;
> +	ring->ptr_mask -= 0x100;
> +
>   	return 0;
>   }
>