[PATCH] drm/amdgpu: support Vega20 A1 ASICs

[Evan Quan]

Since they use different PSP firmwares from A0 ASICs for now.
This will be dropped after they are unified to share the same
PSP firmwares.

Change-Id: I3bc8956dac62607e8771757858b1286a87f76cf3
Signed-off-by: Evan Quan <evan.quan at amd.com>
Acked-by: Alex Deucher <alexander.deucher at amd.com>
---
 drivers/gpu/drm/amd/amdgpu/psp_v11_0.c | 12 +++++++++++-
 1 file changed, 11 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c b/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
index e5dd052d9e06..082093aabaa6 100644
--- a/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
@@ -34,11 +34,14 @@
 #include "nbio/nbio_7_4_offset.h"
 
 MODULE_FIRMWARE("amdgpu/vega20_sos.bin");
+MODULE_FIRMWARE("amdgpu/vega20_sos_old.bin");
 MODULE_FIRMWARE("amdgpu/vega20_ta.bin");
 
 /* address block */
 #define smnMP1_FIRMWARE_FLAGS		0x3010024
 
+#define VEGA20_BL_VERSION_VAR_NEW 0xA1
+
 static int
 psp_v11_0_get_fw_type(struct amdgpu_firmware_info *ucode, enum psp_gfx_fw_type *type)
 {
@@ -101,6 +104,7 @@ static int psp_v11_0_init_microcode(struct psp_context *psp)
 	int err = 0;
 	const struct psp_firmware_header_v1_0 *sos_hdr;
 	const struct ta_firmware_header_v1_0 *ta_hdr;
+	uint32_t bl_version;
 
 	DRM_DEBUG("\n");
 
@@ -112,7 +116,13 @@ static int psp_v11_0_init_microcode(struct psp_context *psp)
 		BUG();
 	}
 
-	snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sos.bin", chip_name);
+	bl_version = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_100);
+	bl_version = (bl_version & 0xFF0000) >> 16;
+
+	if (bl_version == VEGA20_BL_VERSION_VAR_NEW)
+		snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sos.bin", chip_name);
+	else
+		snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sos_old.bin", chip_name);
 	err = request_firmware(&adev->psp.sos_fw, fw_name, adev->dev);
 	if (err)
 		goto out;
-- 
2.19.1