[PATCH] drm/amdgpu/gfx: use proper offset define for MEC doorbells

[Kuehling, Felix]

On 2018-11-16 3:30 p.m., Alex Deucher wrote:
> Looks like a copy paste typo.
>
> Signed-off-by: Alex Deucher <alexander.deucher at amd.com>

Reviewed-by: Felix Kuehling <Felix.Kuehling at amd.com>


> ---
>  drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> index c27caa144c57..e409fbf67fe7 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> @@ -1566,7 +1566,7 @@ static int gfx_v9_0_compute_ring_init(struct amdgpu_device *adev, int ring_id,
>  
>  	ring->ring_obj = NULL;
>  	ring->use_doorbell = true;
> -	ring->doorbell_index = (AMDGPU_DOORBELL_MEC_RING0 + ring_id) << 1;
> +	ring->doorbell_index = (AMDGPU_DOORBELL64_MEC_RING0 + ring_id) << 1;
>  	ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr
>  				+ (ring_id * GFX9_MEC_HPD_SIZE);
>  	sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue);