[PATCH] drm/amdgpu: Enable HDP memory light sleep

[Quan, Evan]

There seems too many " if (adev->asic_type == CHIP_VEGA20)" judgement.
Maybe you can eliminate some or split it into two functions.

Regards,
Evan
> -----Original Message-----
> From: amd-gfx <amd-gfx-bounces at lists.freedesktop.org> On Behalf Of
> Kenneth Feng
> Sent: 2018年11月20日 13:54
> To: amd-gfx at lists.freedesktop.org
> Cc: Feng, Kenneth <Kenneth.Feng at amd.com>
> Subject: [PATCH] drm/amdgpu: Enable HDP memory light sleep
> 
> Due to the register name and setting change of HDP memory light sleep on
> Vega20,change accordingly in the driver.
> 
> Signed-off-by: Kenneth Feng <kenneth.feng at amd.com>
> ---
>  drivers/gpu/drm/amd/amdgpu/soc15.c | 42
> ++++++++++++++++++++++++++++++--------
>  1 file changed, 34 insertions(+), 8 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c
> b/drivers/gpu/drm/amd/amdgpu/soc15.c
> index bf5e6a4..d0fbf66 100644
> --- a/drivers/gpu/drm/amd/amdgpu/soc15.c
> +++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
> @@ -65,6 +65,13 @@
>  #define mmMP0_MISC_LIGHT_SLEEP_CTRL
> 0x01ba
>  #define mmMP0_MISC_LIGHT_SLEEP_CTRL_BASE_IDX
> 0
> 
> +/* for Vega20 register name change */
> +#define mmHDP_MEM_POWER_CTRL	0x00d4
> +#define HDP_MEM_POWER_CTRL__IPH_MEM_POWER_CTRL_EN_MASK
> 	0x00000001L
> +#define HDP_MEM_POWER_CTRL__IPH_MEM_POWER_LS_EN_MASK
> 	0x00000002L
> +#define HDP_MEM_POWER_CTRL__RC_MEM_POWER_CTRL_EN_MASK
> 	0x00010000L
> +#define HDP_MEM_POWER_CTRL__RC_MEM_POWER_LS_EN_MASK
> 		0x00020000L
> +#define mmHDP_MEM_POWER_CTRL_BASE_IDX	0
>  /*
>   * Indirect registers accessor
>   */
> @@ -869,16 +876,35 @@ static int soc15_common_soft_reset(void *handle)
> static void soc15_update_hdp_light_sleep(struct amdgpu_device *adev,
> bool enable)  {
>  	uint32_t def, data;
> -
> -	def = data = RREG32(SOC15_REG_OFFSET(HDP, 0,
> mmHDP_MEM_POWER_LS));
> -
> -	if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS))
> -		data |= HDP_MEM_POWER_LS__LS_ENABLE_MASK;
> +	if (adev->asic_type == CHIP_VEGA20)
> +		def = data = RREG32(SOC15_REG_OFFSET(HDP, 0,
> mmHDP_MEM_POWER_CTRL));
>  	else
> -		data &= ~HDP_MEM_POWER_LS__LS_ENABLE_MASK;
> +		def = data = RREG32(SOC15_REG_OFFSET(HDP, 0,
> mmHDP_MEM_POWER_LS));
> 
> -	if (def != data)
> -		WREG32(SOC15_REG_OFFSET(HDP, 0,
> mmHDP_MEM_POWER_LS), data);
> +	if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS)) {
> +		if (adev->asic_type == CHIP_VEGA20)
> +			data |=
> HDP_MEM_POWER_CTRL__IPH_MEM_POWER_CTRL_EN_MASK |
> +
> 	HDP_MEM_POWER_CTRL__IPH_MEM_POWER_LS_EN_MASK |
> +
> 	HDP_MEM_POWER_CTRL__RC_MEM_POWER_CTRL_EN_MASK |
> +
> 	HDP_MEM_POWER_CTRL__RC_MEM_POWER_LS_EN_MASK;
> +		else
> +			data |= HDP_MEM_POWER_LS__LS_ENABLE_MASK;
> +	} else {
> +		if (adev->asic_type == CHIP_VEGA20)
> +			data &=
> ~(HDP_MEM_POWER_CTRL__IPH_MEM_POWER_CTRL_EN_MASK |
> +
> 	HDP_MEM_POWER_CTRL__IPH_MEM_POWER_LS_EN_MASK |
> +
> 	HDP_MEM_POWER_CTRL__RC_MEM_POWER_CTRL_EN_MASK |
> +
> 	HDP_MEM_POWER_CTRL__RC_MEM_POWER_LS_EN_MASK);
> +		else
> +			data &=
> ~HDP_MEM_POWER_LS__LS_ENABLE_MASK;
> +	}
> +
> +	if (def != data) {
> +		if (adev->asic_type == CHIP_VEGA20)
> +			WREG32(SOC15_REG_OFFSET(HDP, 0,
> mmHDP_MEM_POWER_CTRL), data);
> +		else
> +			WREG32(SOC15_REG_OFFSET(HDP, 0,
> mmHDP_MEM_POWER_LS), data);
> +	}
>  }
> 
>  static void soc15_update_drm_clock_gating(struct amdgpu_device *adev,
> bool enable)
> --
> 2.7.4
> 
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