[PATCH] drm/amdgpu: Add delay after enable RLC ucode
Felix.Kuehling at amd.com
Thu Nov 22 17:18:10 UTC 2018
On 2018-11-22 12:03 p.m., Liu, Shaoyun wrote:
> Driver shouldn't try to access any GFX registers until RLC is idle.
> During the test, it took 12 seconds for RLC to clear the BUSY bit
> in RLC_GPM_STAT register which is un-acceptable for driver.
> As per RLC engineer, it would take RLC Ucode less than 10,000 GFXCLK
> cycles to finish its critical section. In a lowest 300M enginer clock
> setting(default from vbios), 50 us delay is enough.
> Change-Id: If074fbeeecad3f63cf5f5ab232472d0fe46082a6
> Signed-off-by: shaoyunl <shaoyun.liu at amd.com>
> drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 1 +
> 1 file changed, 1 insertion(+)
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> index e409fbf..2e3ee42 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> @@ -2326,6 +2326,7 @@ static void gfx_v9_0_rlc_start(struct amdgpu_device *adev)
> WREG32_FIELD15(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 1);
> + udelay(50);
> /* carrizo do enable cp interrupt after cp inited */
> if (!(adev->flags & AMD_IS_APU))
There is already another udelay(50) here. Is that one still needed?
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