[PATCH] drm/amdgpu: Add delay after enable RLC ucode

[Kuehling, Felix]

On 2018-11-22 1:22 p.m., Liu, Shaoyun wrote:
> Driver shouldn't try to access any GFX registers until RLC is idle.
> During the test, it took 12 seconds for RLC to clear the BUSY bit
> in RLC_GPM_STAT register which is un-acceptable for driver.
> As per RLC engineer, it would take RLC Ucode less than 10,000 GFXCLK
> cycles to finish its critical section. In a lowest 300M enginer clock
> setting(default from vbios), 50 us delay is enough.
>
> Change-Id: If074fbeeecad3f63cf5f5ab232472d0fe46082a6
> Signed-off-by: shaoyunl <shaoyun.liu at amd.com>

See the comment from Ernst Sjöstrand. Other than that, this patch is
Acked-by: Felix Kuehling <Felix.Kuehling at amd.com>

Maybe someone more familiar with the RLC can give a R-B.

Regards,
  Felix


> ---
>  drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 7 ++++---
>  1 file changed, 4 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> index e409fbf..9686fcc 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> @@ -2326,12 +2326,13 @@ static void gfx_v9_0_rlc_start(struct amdgpu_device *adev)
>  #endif
>  
>  	WREG32_FIELD15(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 1);
> +	udelay(50);
>  
>  	/* carrizo do enable cp interrupt after cp inited */
> -	if (!(adev->flags & AMD_IS_APU))
> +	if (!(adev->flags & AMD_IS_APU)) {
>  		gfx_v9_0_enable_gui_idle_interrupt(adev, true);
> -
> -	udelay(50);
> +		udelay(50);
> +	}
>  
>  #ifdef AMDGPU_RLC_DEBUG_RETRY
>  	/* RLC_GPM_GENERAL_6 : RLC Ucode version */