[PATCH] drm/amd/display: limit high pixel clock modes on ST/CZ

Deucher, Alexander Alexander.Deucher at amd.com
Mon Nov 26 14:15:50 UTC 2018

I thought there was a patch to do this already that got sent out a few weeks ago.  Basically limit ST/CZ to modes that do not require a retimer.  Is an additional patch needed?


From: amd-gfx <amd-gfx-bounces at lists.freedesktop.org> on behalf of S, Shirish <Shirish.S at amd.com>
Sent: Monday, November 26, 2018 1:36:30 AM
To: Li, Sun peng (Leo); Wentland, Harry
Cc: amd-gfx at lists.freedesktop.org; S, Shirish
Subject: [PATCH] drm/amd/display: limit high pixel clock modes on ST/CZ

ST/CZ (dce110) advertises modes such as 4k at 60Hz etc.,
that it cannot handle correctly, hence  resulting in
several issues like flickering, black lines/flashes and so on.

These modes are basically high pixel clock ones, hence
limit the same to be advertised to avoid bad user experiences

Signed-off-by: Shirish S <shirish.s at amd.com>
Suggested-by: Harry Wentland <harry.wentland at amd.com>
 .../gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c    | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c
index 1b2fe0d..1b8fe99 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c
@@ -1121,6 +1121,16 @@ bool dce110_timing_generator_validate_timing(
         if (!timing)
                 return false;

+       /* Limit all modes that have a high pixel clock
+        * which seems to be problematic on dce110
+        * These include: 4k at 60Hz, 1080p at 144Hz,1440p at 120Hz
+        * based on the below formula:
+        * refresh rate = pixel clock / (htotal * vtotal)
+        */
+       if (timing->pix_clk_khz > 300000)
+               return false;
         hsync_offset = timing->h_border_right + timing->h_front_porch;
         h_sync_start = timing->h_addressable + hsync_offset;


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