[PATCH] drm/amd/display: Fix 6x4K displays light-up on Vega20

[Roman.Li at amd.com]

From: Roman Li <Roman.Li at amd.com>

[Why]
More than 4x4K didn't lightup on Vega20 due to low dcfclk value.
Powerplay expects valid min requirement for dcfclk from DC.

[How]
Update min_dcfclock_khz based on min_engine_clock value.

Change-Id: I123f5f98cb02fc8cb5e3c9ea619efc8aa5aa4463
Reviewed-by: Hersen Wu <hersenxs.wu at amd.com>
Reviewed-by: Feifei Xu <Feifei.Xu at amd.com>
Reviewed-by: Evan Quan <evan.quan at amd.com>
Acked-by: Alex Deucher <alexander.deucher at amd.com>
Signed-off-by: Roman Li <Roman.Li at amd.com>
---
 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c
index 56f5985..bd22f51 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c
@@ -591,6 +591,8 @@ static void dce11_pplib_apply_display_requirements(
 			dc,
 			context->bw.dce.sclk_khz);
 
+	pp_display_cfg->min_dcfclock_khz = pp_display_cfg->min_engine_clock_khz;
+
 	pp_display_cfg->min_engine_clock_deep_sleep_khz
 			= context->bw.dce.sclk_deep_sleep_khz;
 
-- 
2.7.4