[PATCH] drm/amdgpu:Replace value with defined macro

[Leo Liu]

On 10/02/2018 01:20 PM, James Zhu wrote:
> Replace value with defined macro to make
> code more readable
>
> Signed-off-by: James Zhu <James.Zhu at amd.com>
> ---
>   drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c |  7 +++++--
>   drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c   | 12 +++++++-----
>   2 files changed, 12 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
> index 12a60ec..7ad352c 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
> @@ -309,14 +309,17 @@ static int amdgpu_vcn_pause_dpg_mode(struct amdgpu_device *adev,
>   				/* Restore */
>   				ring = &adev->vcn.ring_jpeg;
>   				WREG32_SOC15(UVD, 0, mmUVD_LMI_JRBC_RB_VMID, 0);
> -				WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_CNTL, 0x00000001L | 0x00000002L);
> +				WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_CNTL,
> +							UVD_JRBC_RB_CNTL__RB_NO_FETCH_MASK |
> +							UVD_JRBC_RB_CNTL__RB_RPTR_WR_EN_MASK);
Please use same indentation like below. With that fixed, the patch is
Acked-by: Leo Liu <leo.liu at amd.com>



>   				WREG32_SOC15(UVD, 0, mmUVD_LMI_JRBC_RB_64BIT_BAR_LOW,
>   					     lower_32_bits(ring->gpu_addr));
>   				WREG32_SOC15(UVD, 0, mmUVD_LMI_JRBC_RB_64BIT_BAR_HIGH,
>   					     upper_32_bits(ring->gpu_addr));
>   				WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_RPTR, ring->wptr);
>   				WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_WPTR, ring->wptr);
> -				WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_CNTL, 0x00000002L);
> +				WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_CNTL,
> +							UVD_JRBC_RB_CNTL__RB_RPTR_WR_EN_MASK);
>   
>   				ring = &adev->vcn.ring_dec;
>   				WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR,
> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
> index 78a3115b..8c53fb4 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
> @@ -810,12 +810,12 @@ static int vcn_v1_0_start_spg_mode(struct amdgpu_device *adev)
>   
>   		for (j = 0; j < 100; ++j) {
>   			status = RREG32_SOC15(UVD, 0, mmUVD_STATUS);
> -			if (status & 2)
> +			if (status & UVD_STATUS__IDLE)
>   				break;
>   			mdelay(10);
>   		}
>   		r = 0;
> -		if (status & 2)
> +		if (status & UVD_STATUS__IDLE)
>   			break;
>   
>   		DRM_ERROR("VCN decode not responding, trying to reset the VCPU!!!\n");
> @@ -898,12 +898,13 @@ static int vcn_v1_0_start_spg_mode(struct amdgpu_device *adev)
>   
>   	ring = &adev->vcn.ring_jpeg;
>   	WREG32_SOC15(UVD, 0, mmUVD_LMI_JRBC_RB_VMID, 0);
> -	WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_CNTL, (0x00000001L | 0x00000002L));
> +	WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_CNTL, UVD_JRBC_RB_CNTL__RB_NO_FETCH_MASK |
> +			UVD_JRBC_RB_CNTL__RB_RPTR_WR_EN_MASK);
>   	WREG32_SOC15(UVD, 0, mmUVD_LMI_JRBC_RB_64BIT_BAR_LOW, lower_32_bits(ring->gpu_addr));
>   	WREG32_SOC15(UVD, 0, mmUVD_LMI_JRBC_RB_64BIT_BAR_HIGH, upper_32_bits(ring->gpu_addr));
>   	WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_RPTR, 0);
>   	WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_WPTR, 0);
> -	WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_CNTL, 0x00000002L);
> +	WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_CNTL, UVD_JRBC_RB_CNTL__RB_RPTR_WR_EN_MASK);
>   
>   	/* initialize wptr */
>   	ring->wptr = RREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_WPTR);
> @@ -1123,7 +1124,8 @@ static int vcn_v1_0_stop_dpg_mode(struct amdgpu_device *adev)
>   	int ret_code;
>   
>   	/* Wait for power status to be 1 */
> -	SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS, 0x1,
> +	SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS,
> +			UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF,
>   			UVD_POWER_STATUS__UVD_POWER_STATUS_MASK, ret_code);
>   
>   	/* disable dynamic power gating mode */