[RFC] drm/amd/display: add SI support to AMD DC

[Mike Lothian]

Hi Mauro

Do you know if there are any plans to add in UVD support on SI too?

Thanks

Mike

On Mon, 8 Oct 2018 at 03:24 Mauro Rossi <issor.oruam at gmail.com> wrote:

> [PATCH 01/10] drm/amd/display: add asics info for SI parts
> [PATCH 02/10] drm/amd/display: dc/dce: add DCE6 support
> [PATCH 03/10] drm/amd/display: dc/core: add DCE6 support
> [PATCH 04/10] drm/amd/display: dc/bios: add support for DCE6
> [PATCH 05/10] drm/amd/display: dc/gpio: add support for DCE6
> [PATCH 06/10] drm/amd/display: dc/i2caux: add support for DCE6
> [PATCH 07/10] drm/amd/display: dc/irq: add support for DCE6
> [PATCH 08/10] drm/amd/display: amdgpu_dm: add SI support
> [PATCH 09/10] drm/amdgpu: enable DC support for SI parts
> [PATCH 10/10] drm/amd/display: enable SI support in the Kconfig
>
> The series adds preliminar SI support as a Proof Of Concept,
> based on the idea that DCE6 is similar to DCE8, to be reviewed and refined
>
> Android-x86 need/motivation lies in the following chain of dependencies:
> Vulkan radv requires gbm gralloc prime_fd support,
> gbm gralloc requires drm hwcomposer,
> drm hwcomposer requires Atomic Display Framework,
> Atomic Display Framework requires AMD DC, currently not supporting SI.
>
> So the goals are:
> 1) to get Vulkan radv working on SI parts for android-x86.
> 2) to remove the gap in SI (GCN 1st gen) not having atomic support.
>
> DCE6 specific code was implemented as a replica of existing DCE8 support
> and based on how DCE8 specific code was added on top of DCE10,11 support
> by adding dce60* sources, functions, macros for each existing in dce80*
>
> CONFIG_DRM_AMD_DC_SI parameter has been added to control SI support in DC
>
> During this first iteration of review, there are aspects to verify:
> - dce60 code has been added mechanically, so there may be redundancies
> and space for refactoring part of the code
> - dce60_resources was having too many building errors due to missing DCE6
> macros
> in order to temporarily overcome the problem dce_8_0_{d,sh_mask}.h headers
> were used for the PoC
> - dc/irq suffered the same problem dce_8_0_{d,sh_mask}.h headers
> were used for the PoC
> - gfx6 may require some ad hoc initialization, skipped for the moment
> - Hainan specific code requires review, as some documentation and code
> paths
> seem to point that famility may not have DCE6, please confirm
> - video decoding blocks code have not been touched
> - dc/dce/dce_clock_source.{c,h} may be missing some SI/DCE6 specifics
> - dc/dce/dce_dmcu.{c,h} may be missing some SI/DCE6 specifics
> - dc/dce/dce_hwseq.h may be missing some SI/DCE6 specifics
> - dc/dce/dce_link_encoder.h may be missing some SI/DCE6 specifics
> - dc/dce/dce_stream_encoder.h may be missing some SI/DCE6 specifics
> - dc/amdgpu_dm/* changes may be incomplete
> - Any other omissis to be reviewed
> - Feedback on best testing strategy required
>
> Review from an expert of the DC impacted modules is recommended
>
>     SW Layer
> /===============================================================\
> | DC        Display     Timing          Mode        Asic        |
> | Interface Service     Service         Manager     Capability* |
> |                                                               |
> | Display   Topology    Display         Link        Adapter     |
> | Path      Manager     Capability      Service     Service     |
> |                       Service                                 |
> |---------------------------------------------------------------|
> | GPIO*     IRQ         I2cAux          HW          BIOS        |
> |           Service**   Manager*        Sequencer*  Parser*     |
> |                                                               |
> | Connector Encoder     Audio           GPU         Controller  |
> |                                                               |
> \===============================================================/
>     HW Layer
>
> Legend:
> *dce60 support was added cleanly with dce_6_0_{d,sh_mask}.h headers
> **dce60 support was added using dce_8_0_{d,sh_mask}.h headers
>
> Android-x86 preliminary tests results:
>
> [Boots with drm gralloc]
> 3DMark Slingshot
> GFXbench OpenGLES benchmarks OK
> V1 GPU benchmark (OpenGLES) OK
> Regression in Google Chrome, Youtube (app does not show up)
> Regression in Olympus Rising,  Chicken Invaders (app does not show up)
>
> [Boots with drm hwcomposer + gbm gralloc]
> Google Chrome, Youtube are OK
> Vulkan radv HAL API becomes available with hwc+gbm gralloc
> V1 GPU benchmark (Vulkan API) OK
> Sacha Willems examples OK
> Some glitch/freeze in 3DMark Slingshot Extreeme and API overhead
>
> Kind regards
>
> Mauro Rossi
> android-x86 team
>
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