[PATCH 1/2] drm/amdgpu: add CP_DEBUG register definition for GC9.0

[Christian König]

Am 09.10.2018 um 08:31 schrieb tao.zhou1 at amd.com:
> From: Tao Zhou <tao.zhou1 at amd.com>
>
> Add CP_DEBUG register definition.
>
> Change-Id: I38b0e5accc9ed2f516f409f1ffd88a9690356083
> Signed-off-by: Tao Zhou <tao.zhou1 at amd.com>

Acked-by: Christian König <christian.koenig at amd.com> for the series.

> ---
>   drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h | 2 ++
>   1 file changed, 2 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h
> index 4ce090d..529b37d 100644
> --- a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h
> +++ b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h
> @@ -2449,6 +2449,8 @@
>   #define mmCP_ECC_FIRSTOCCURRENCE_RING2_BASE_IDX                                                        0
>   #define mmGB_EDC_MODE                                                                                  0x107e
>   #define mmGB_EDC_MODE_BASE_IDX                                                                         0
> +#define mmCP_DEBUG                                                                                     0x107f
> +#define mmCP_DEBUG_BASE_IDX                                                                            0
>   #define mmCP_CPF_DEBUG                                                                                 0x1080
>   #define mmCP_PQ_WPTR_POLL_CNTL                                                                         0x1083
>   #define mmCP_PQ_WPTR_POLL_CNTL_BASE_IDX                                                                0