[PATCH 5/5] drm/amdgpu/rlc: gfx_v9 change the method to call rlc function

[likun Gao]

From: Likun Gao <Likun.Gao at amd.com>

Use struct pointer to call rlc function.

Signed-off-by: Likun Gao <Likun.Gao at amd.com>
---
 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 30 ++++++++++++++++++------------
 1 file changed, 18 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index d6b5069..16798f7 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -1152,7 +1152,7 @@ static int gfx_v9_0_rlc_init(struct amdgpu_device *adev)
 		if (r) {
 			dev_err(adev->dev, "(%d) failed to create rlc csb bo\n",
 				r);
-			gfx_v9_0_rlc_fini(adev);
+			adev->gfx.rlc.funcs->rlc_fini(adev);
 			return r;
 		}
 		/* set up the cs buffer */
@@ -1174,7 +1174,7 @@ static int gfx_v9_0_rlc_init(struct amdgpu_device *adev)
 		if (r) {
 			dev_err(adev->dev,
 				"(%d) failed to create cp table bo\n", r);
-			gfx_v9_0_rlc_fini(adev);
+			adev->gfx.rlc.funcs->rlc_fini(adev);
 			return r;
 		}
 
@@ -1738,7 +1738,7 @@ static int gfx_v9_0_sw_init(void *handle)
 		return r;
 	}
 
-	r = gfx_v9_0_rlc_init(adev);
+	r = adev->gfx.rlc.funcs->rlc_init(adev);
 	if (r) {
 		DRM_ERROR("Failed to init rlc BOs!\n");
 		return r;
@@ -2488,12 +2488,12 @@ static int gfx_v9_0_rlc_resume(struct amdgpu_device *adev)
 		return 0;
 	}
 
-	gfx_v9_0_rlc_stop(adev);
+	adev->gfx.rlc.funcs->rlc_stop(adev);
 
 	/* disable CG */
 	WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, 0);
 
-	gfx_v9_0_rlc_reset(adev);
+	adev->gfx.rlc.funcs->rlc_reset(adev);
 
 	gfx_v9_0_init_pg(adev);
 
@@ -2512,7 +2512,7 @@ static int gfx_v9_0_rlc_resume(struct amdgpu_device *adev)
 			gfx_v9_0_enable_lbpw(adev, false);
 	}
 
-	gfx_v9_0_rlc_start(adev);
+	adev->gfx.rlc.funcs->rlc_start(adev);
 
 	return 0;
 }
@@ -3343,7 +3343,7 @@ static int gfx_v9_0_hw_init(void *handle)
 	if (r)
 		return r;
 
-	r = gfx_v9_0_rlc_resume(adev);
+	r = adev->gfx.rlc.funcs->rlc_resume(adev);
 	if (r)
 		return r;
 
@@ -3423,7 +3423,7 @@ static int gfx_v9_0_hw_fini(void *handle)
 	}
 
 	gfx_v9_0_cp_enable(adev, false);
-	gfx_v9_0_rlc_stop(adev);
+	adev->gfx.rlc.funcs->rlc_stop(adev);
 
 	gfx_v9_0_csb_vram_unpin(adev);
 
@@ -3498,7 +3498,7 @@ static int gfx_v9_0_soft_reset(void *handle)
 
 	if (grbm_soft_reset) {
 		/* stop the rlc */
-		gfx_v9_0_rlc_stop(adev);
+		adev->gfx.rlc.funcs->rlc_stop(adev);
 
 		/* Disable GFX parsing/prefetching */
 		gfx_v9_0_cp_gfx_enable(adev, false);
@@ -3654,7 +3654,7 @@ static void gfx_v9_0_exit_rlc_safe_mode(struct amdgpu_device *adev)
 static void gfx_v9_0_update_gfx_cg_power_gating(struct amdgpu_device *adev,
 						bool enable)
 {
-	gfx_v9_0_enter_rlc_safe_mode(adev);
+	adev->gfx.rlc.funcs->enter_safe_mode(adev);
 
 	if ((adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) && enable) {
 		gfx_v9_0_enable_gfx_cg_power_gating(adev, true);
@@ -3665,7 +3665,7 @@ static void gfx_v9_0_update_gfx_cg_power_gating(struct amdgpu_device *adev,
 		gfx_v9_0_enable_gfx_pipeline_powergating(adev, false);
 	}
 
-	gfx_v9_0_exit_rlc_safe_mode(adev);
+	adev->gfx.rlc.funcs->exit_safe_mode(adev);
 }
 
 static void gfx_v9_0_update_gfx_mg_power_gating(struct amdgpu_device *adev,
@@ -3881,7 +3881,13 @@ static int gfx_v9_0_update_gfx_clock_gating(struct amdgpu_device *adev,
 
 static const struct amdgpu_rlc_funcs gfx_v9_0_rlc_funcs = {
 	.enter_safe_mode = gfx_v9_0_enter_rlc_safe_mode,
-	.exit_safe_mode = gfx_v9_0_exit_rlc_safe_mode
+	.exit_safe_mode = gfx_v9_0_exit_rlc_safe_mode,
+	.rlc_init = gfx_v9_0_rlc_init,
+	.rlc_fini = gfx_v9_0_rlc_fini,
+	.rlc_resume = gfx_v9_0_rlc_resume,
+	.rlc_stop = gfx_v9_0_rlc_stop,
+	.rlc_reset = gfx_v9_0_rlc_reset,
+	.rlc_start = gfx_v9_0_rlc_start
 };
 
 static int gfx_v9_0_set_powergating_state(void *handle,
-- 
2.7.4