[PATCH] drm/amdgpu/sriov: Set the default value about gds vmid0 size
Deng, Emily
Emily.Deng at amd.com
Fri Oct 12 05:51:08 UTC 2018
>-----Original Message-----
>From: Zhang, Jerry
>Sent: Friday, October 12, 2018 1:18 PM
>To: Deng, Emily <Emily.Deng at amd.com>; amd-gfx at lists.freedesktop.org
>Subject: Re: [PATCH] drm/amdgpu/sriov: Set the default value about gds
>vmid0 size
>
>On 10/12/2018 11:21 AM, Emily Deng wrote:
>> For sriov, when first run windows guest, then run linux guest, the gds
>> vmid0 size will be reset to 0 by windows guest. So if the value has
>> been reset to 0, then set the value to the default value in linux guest.
>>
>> Signed-off-by: Emily Deng <Emily.Deng at amd.com>
>> ---
>> drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 14 ++++++++++++++
>> 1 file changed, 14 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
>> b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
>> index ae86238..d9df3dd 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
>> @@ -4872,6 +4872,17 @@ static void gfx_v9_0_set_rlc_funcs(struct
>amdgpu_device *adev)
>> }
>> }
>>
>> +static void gfx_v9_0_set_gds_default(struct amdgpu_device *adev) {
>> + switch (adev->asic_type) {
>> + case CHIP_VEGA10:
>> + adev->gds.mem.total_size = 0x10000;
>Do you mean this value is same as the original value from
>mmGDS_VMID0_SIZE before reset?
>if so, we may provide a default value for recovery, e.g. in the gds.mem
>structure.
Yes.
>Regards,
>Jerry
>> + break;
>> + default:
>> + break;
>> + }
>> +}
>> +
>> static void gfx_v9_0_set_gds_init(struct amdgpu_device *adev)
>> {
>> /* init asci gds info */
>> @@ -4879,6 +4890,9 @@ static void gfx_v9_0_set_gds_init(struct
>amdgpu_device *adev)
>> adev->gds.gws.total_size = 64;
>> adev->gds.oa.total_size = 16;
>>
>> + if (adev->gds.mem.total_size == 0 && amdgpu_sriov_vf(adev))
>> + gfx_v9_0_set_gds_default(adev);
>> +
>> if (adev->gds.mem.total_size == 64 * 1024) {
>> adev->gds.mem.gfx_partition_size = 4096;
>> adev->gds.mem.cs_partition_size = 4096;
More information about the amd-gfx
mailing list