[PATCH] drm/amd/powerplay: fix compile warning for wrong data type

[Evan Quan]

do_div expects the 1st argument in 64bit instead of 32bit.

Change-Id: Id2032a43727e7f1fa5163333d3565354d412a561
Signed-off-by: Evan Quan <evan.quan at amd.com>
---
 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
index 3efd59e984a3..6ba5f328249d 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
@@ -1191,14 +1191,14 @@ static int vega20_set_sclk_od(
 			&(data->dpm_table.gfx_table);
 	struct vega20_single_dpm_table *golden_sclk_table =
 			&(data->golden_dpm_table.gfx_table);
-	uint32_t od_sclk;
+	uint64_t od_sclk;
 	int ret = 0;
 
 	od_sclk = golden_sclk_table->dpm_levels[golden_sclk_table->count - 1].value * value;
 	do_div(od_sclk, 100);
 	od_sclk += golden_sclk_table->dpm_levels[golden_sclk_table->count - 1].value;
 
-	ret = vega20_od8_set_settings(hwmgr, OD8_SETTING_GFXCLK_FMAX, od_sclk);
+	ret = vega20_od8_set_settings(hwmgr, OD8_SETTING_GFXCLK_FMAX, (uint32_t)od_sclk);
 	PP_ASSERT_WITH_CODE(!ret,
 			"[SetSclkOD] failed to set od gfxclk!",
 			return ret);
@@ -1238,14 +1238,14 @@ static int vega20_set_mclk_od(
 			&(data->dpm_table.mem_table);
 	struct vega20_single_dpm_table *golden_mclk_table =
 			&(data->golden_dpm_table.mem_table);
-	uint32_t od_mclk;
+	uint64_t od_mclk;
 	int ret = 0;
 
 	od_mclk = golden_mclk_table->dpm_levels[golden_mclk_table->count - 1].value * value;
 	do_div(od_mclk, 100);
 	od_mclk += golden_mclk_table->dpm_levels[golden_mclk_table->count - 1].value;
 
-	ret = vega20_od8_set_settings(hwmgr, OD8_SETTING_UCLK_FMAX, od_mclk);
+	ret = vega20_od8_set_settings(hwmgr, OD8_SETTING_UCLK_FMAX, (uint32_t)od_mclk);
 	PP_ASSERT_WITH_CODE(!ret,
 			"[SetMclkOD] failed to set od memclk!",
 			return ret);
-- 
2.18.0