[RFC] drm/amdgpu: Add macros and documentation for format modifiers.

[Bas Nieuwenhuizen]

On Fri, Sep 7, 2018 at 6:51 AM Marek Olšák <maraeo at gmail.com> wrote:
>
> Hopefully this answers some questions.
>
> Other parameters that affect tiling layouts are GB_ADDR_CONFIG (all
> chips) and MC_ARB_RAMCFG (GFX6-8 only), and those vary with each chip.

For GFX6-GFX8:
>From GB_ADDR_CONFIG addrlib only uses the pipe interleave bytes which
are 0 (=256 bytes) for all AMDGPU HW (and on GFX9 addrlib even asserts
on that).  From MC_ARB_RAMCFG addrlib reads the number of banks and
ranks, calculates the number of logical banks from it, but then does
not use it. (Presumably because it is the same number as the number of
banks in the tiling table entry?) Some bits gets used by the kernel
(memory row size), but those get encoded in the tile split of the
tiling table, i.e. we do not need the separate bits.

for GFX9, only the DCC meta surface seems to depend on GB_ADDR_CONFIG
(except the aforementioned pipe interleave bytes) which are constant.

I'll do some checks to see if we can trust addrlib here.

>
> Some 32bpp 1D tiling layouts are compatible across all chips (1D
> display tiling is the same as SW_256B_D if Bpp == 4).

Cool hadn't seen that they were equivalent in some situations.

>
> On GFX9, swizzle modes <= 11 are the same on all GFX9 chips. The
> remaining modes depend on GB_ADDR_CONFIG and are also more efficient.
> Bpp, number of samples, and resource type (2D/3D) affect the layout
> too, e.g. 3D textures silently use thick tiling on GFX9.
>
> Harvesting doesn't affect tiling layouts.
>
> The layout changes between layers/slices a little. Always use the base
> address of the whole image when programming the hardware. Don't assume
> that the 2nd layer has the same layout.
>
> > + * TODO: Can scanout really not support fastclear data?
>
> It can, but only those encoded in the DCC buffer (0/1). There is no
> DAL support for DCC though.
>
>
> > + * TODO: Do some generations share DCC format?
>
> DCC mirrors the tiling layout, so the same tiling mode means the same
> DCC. Take the absolute pixel address, shift it to the right, and
> you'll get the DCC element address.
>
> I would generally consider DCC as non-shareable because of different
> meanings of TILING_INDEX between chips except maybe for common GFX9
> layouts.

I was also thinking about the compression changes on Polaris that
improved compression. I'm not sure if that added e.g. new encodings in
how we store the data of a DCC tile in the main data surface.
>
>
> > [comments about number of bits]
>
> We could certainly represent all formats as a list of enums, but then
> we would need to convert the enums to the full description in drivers.
> GFX6-8 can use TILING_INDEX (except for stencil, let's ignore
> stencil). The tiling tables shouldn't change anymore because they are
> optimized for the hardware, and later hw doesn't have any tables.
>
> Marek