[PATCH 4/7] drm/amd/pp: Remove wrong code in fiji_start_smu

[Alex Deucher]

On Wed, Sep 26, 2018 at 8:52 AM Rex Zhu <Rex.Zhu at amd.com> wrote:
>
> HW CG feature will be enabled after hw ip initialized
>
> Signed-off-by: Rex Zhu <Rex.Zhu at amd.com>

Reviewed-by: Alex Deucher <alexander.deucher at amd.com>

> ---
>  drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c | 10 ----------
>  1 file changed, 10 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c
> index ec14798..b6b62a7 100644
> --- a/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c
> @@ -302,16 +302,6 @@ static int fiji_start_smu(struct pp_hwmgr *hwmgr)
>                         hwmgr->avfs_supported = false;
>         }
>
> -       /* To initialize all clock gating before RLC loaded and running.*/
> -       amdgpu_device_ip_set_clockgating_state(hwmgr->adev,
> -                       AMD_IP_BLOCK_TYPE_GFX, AMD_CG_STATE_GATE);
> -       amdgpu_device_ip_set_clockgating_state(hwmgr->adev,
> -                       AMD_IP_BLOCK_TYPE_GMC, AMD_CG_STATE_GATE);
> -       amdgpu_device_ip_set_clockgating_state(hwmgr->adev,
> -                       AMD_IP_BLOCK_TYPE_SDMA, AMD_CG_STATE_GATE);
> -       amdgpu_device_ip_set_clockgating_state(hwmgr->adev,
> -                       AMD_IP_BLOCK_TYPE_COMMON, AMD_CG_STATE_GATE);
> -
>         /* Setup SoftRegsStart here for register lookup in case
>          * DummyBackEnd is used and ProcessFirmwareHeader is not executed
>          */
> --
> 1.9.1
>
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