[PATCH] drm/amdgpu: change encode ib size alignment to 4 bytes

[Christian König]

Am 15.04.19 um 16:23 schrieb boyuan.zhang at amd.com:
> From: Boyuan Zhang <boyuan.zhang at amd.com>
>
> All encode ibs must be dword aligned for address/size.
>
> It's been working because all ib based addresses are normally page aligned,
> and all encode FW interface structure sizes are dword aligned. However, it might
> cause issue when UMD tries to align size based on alignment reported by kernel.
>
> Signed-off-by: Boyuan Zhang <boyuan.zhang at amd.com>

Acked-by: Christian König <christian.koenig at amd.com>

> ---
>   drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 6 +++---
>   1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
> index 8ced7841c23f..33cf95a72e6a 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
> @@ -387,7 +387,7 @@ static int amdgpu_hw_ip_info(struct amdgpu_device *adev,
>   			if (adev->vce.ring[i].sched.ready)
>   				++num_rings;
>   		ib_start_alignment = 4;
> -		ib_size_alignment = 1;
> +		ib_size_alignment = 4;
>   		break;
>   	case AMDGPU_HW_IP_UVD_ENC:
>   		type = AMD_IP_BLOCK_TYPE_UVD;
> @@ -400,7 +400,7 @@ static int amdgpu_hw_ip_info(struct amdgpu_device *adev,
>   					++num_rings;
>   		}
>   		ib_start_alignment = 64;
> -		ib_size_alignment = 64;
> +		ib_size_alignment = 4;
>   		break;
>   	case AMDGPU_HW_IP_VCN_DEC:
>   		type = AMD_IP_BLOCK_TYPE_VCN;
> @@ -415,7 +415,7 @@ static int amdgpu_hw_ip_info(struct amdgpu_device *adev,
>   			if (adev->vcn.ring_enc[i].sched.ready)
>   				++num_rings;
>   		ib_start_alignment = 64;
> -		ib_size_alignment = 1;
> +		ib_size_alignment = 4;
>   		break;
>   	case AMDGPU_HW_IP_VCN_JPEG:
>   		type = AMD_IP_BLOCK_TYPE_VCN;