[PATCH 1/2] SWDEV-183622 4k at 60hz dp monitor always flicking

[Gao, Likun]

Patch is Tested-by: Likun Gao <Likun.Gao at amd.com>

-----Original Message-----
From: amd-gfx <amd-gfx-bounces at lists.freedesktop.org> On Behalf Of Huang, Ray
Sent: Wednesday, April 17, 2019 2:26 PM
To: Wu, Hersen <hersenxs.wu at amd.com>; amd-gfx at lists.freedesktop.org; Deucher, Alexander <Alexander.Deucher at amd.com>
Cc: Wu, Hersen <hersenxs.wu at amd.com>
Subject: RE: [PATCH 1/2] SWDEV-183622 4k at 60hz dp monitor always flicking

> -----Original Message-----
> From: amd-gfx [mailto:amd-gfx-bounces at lists.freedesktop.org] On Behalf 
> Of hersen wu
> Sent: Monday, April 15, 2019 10:18 PM
> To: amd-gfx at lists.freedesktop.org; Deucher, Alexander 
> <Alexander.Deucher at amd.com>
> Cc: Wu, Hersen <hersenxs.wu at amd.com>
> Subject: [PATCH 1/2] SWDEV-183622 4k at 60hz dp monitor always flicking
> 
> [WHY] clock unit mis-match between caller DC and SMU interface.
>       dc pass lock in mhz. the same unit as smu. no covert is needed.
> 
> [HOW] remove covert_10k_to_mhz in smu interface
>       this fixes corruption issue with 4k @60 display and stutter
>       mode enable
> 
> Signed-off-by: hersen wu <hersenxs.wu at amd.com>

We would better not to expose internal ticket (SWDEV-183622) to public. 

Shall we modify the patch title as "drm/amd/powerplay: fix the issue that 4k at 60hz dp monitor always flicking"

With that fixed, patch is Reviewed-by: Huang Rui <ray.huang at amd.com>

> ---
>  .../gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c   | 17 ++++++----------
> -
>  1 file changed, 6 insertions(+), 11 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
> b/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
> index f32e3d0aaea6..078613348e78 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
> @@ -204,18 +204,13 @@ static int smu10_set_clock_limit(struct pp_hwmgr 
> *hwmgr, const void *input)
>  	return 0;
>  }
> 
> -static inline uint32_t convert_10k_to_mhz(uint32_t clock) -{
> -	return (clock + 99) / 100;
> -}
> -
>  static int smu10_set_min_deep_sleep_dcefclk(struct pp_hwmgr *hwmgr, 
> uint32_t clock)  {
>  	struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr 
> *)(hwmgr->backend);
> 
>  	if (smu10_data->need_min_deep_sleep_dcefclk &&
> -		smu10_data->deep_sleep_dcefclk !=
> convert_10k_to_mhz(clock)) {
> -		smu10_data->deep_sleep_dcefclk =
> convert_10k_to_mhz(clock);
> +		smu10_data->deep_sleep_dcefclk != clock) {
> +		smu10_data->deep_sleep_dcefclk = clock;
>  		smum_send_msg_to_smc_with_parameter(hwmgr,
> 
> 	PPSMC_MSG_SetMinDeepSleepDcefclk,
>  					smu10_data->deep_sleep_dcefclk); @@ -228,8 +223,8 @@ static int 
> smu10_set_hard_min_dcefclk_by_freq(struct pp_hwmgr *hwmgr, uint32_t c
>  	struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr 
> *)(hwmgr->backend);
> 
>  	if (smu10_data->dcf_actual_hard_min_freq &&
> -		smu10_data->dcf_actual_hard_min_freq !=
> convert_10k_to_mhz(clock)) {
> -		smu10_data->dcf_actual_hard_min_freq =
> convert_10k_to_mhz(clock);
> +		smu10_data->dcf_actual_hard_min_freq != clock) {
> +		smu10_data->dcf_actual_hard_min_freq = clock;
>  		smum_send_msg_to_smc_with_parameter(hwmgr,
> 
> 	PPSMC_MSG_SetHardMinDcefclkByFreq,
>  					smu10_data-
> >dcf_actual_hard_min_freq);
> @@ -242,8 +237,8 @@ static int smu10_set_hard_min_fclk_by_freq(struct
> pp_hwmgr *hwmgr, uint32_t cloc
>  	struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr 
> *)(hwmgr->backend);
> 
>  	if (smu10_data->f_actual_hard_min_freq &&
> -		smu10_data->f_actual_hard_min_freq !=
> convert_10k_to_mhz(clock)) {
> -		smu10_data->f_actual_hard_min_freq =
> convert_10k_to_mhz(clock);
> +		smu10_data->f_actual_hard_min_freq != clock) {
> +		smu10_data->f_actual_hard_min_freq = clock;
>  		smum_send_msg_to_smc_with_parameter(hwmgr,
>  					PPSMC_MSG_SetHardMinFclkByFreq,
>  					smu10_data-
> >f_actual_hard_min_freq);
> --
> 2.17.1
> 
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