[PATCH] drm/amdgpu: remove unpin clear_state_obj for gfx v8

[Gao, Likun]

OK, thanks, will try to fix with that method.

Regards,
Likun

-----Original Message-----
From: Yuan, Xiaojie <Xiaojie.Yuan at amd.com> 
Sent: Friday, August 2, 2019 2:12 PM
To: Gao, Likun <Likun.Gao at amd.com>; amd-gfx at lists.freedesktop.org
Cc: Deucher, Alexander <Alexander.Deucher at amd.com>; Paul Gover <pmw.gover at yahoo.co.uk>
Subject: Re: [PATCH] drm/amdgpu: remove unpin clear_state_obj for gfx v8

Hi Likun,

Looks like you can pin csb buffer @gfx_v8_0_hw_init() just like what following patch does for gfx9, so that we can still use the common function amdgpu_gfx_rlc_init_csb():

commit 137dc4b9060e99a22dce59b42ca71912cf0180f3
Author: Evan Quan <evan.quan at amd.com>
Date:   Wed Jul 4 16:21:52 2018 +0800

    drm/amdgpu: pin the csb buffer on hw init v2

    Without this pin, the csb buffer will be filled with inconsistent
    data after S3 resume. And that will causes gfx hang on gfxoff
    exit since this csb will be executed then.

    v2: fit amdgpu_bo_pin change(take one less argument)

    Signed-off-by: Evan Quan <evan.quan at amd.com>
    Reviewed-by: Huang Rui <ray.huang at amd.com>
    Signed-off-by: Alex Deucher <alexander.deucher at amd.com>

BR,
Xiaojie

________________________________________
From: amd-gfx <amd-gfx-bounces at lists.freedesktop.org> on behalf of likun Gao <likun.gao at amd.com>
Sent: Friday, August 2, 2019 1:22 PM
To: amd-gfx at lists.freedesktop.org
Cc: Deucher, Alexander; Gao, Likun; Paul Gover
Subject: [PATCH] drm/amdgpu: remove unpin clear_state_obj for gfx v8

From: Likun Gao <Likun.Gao at amd.com>

Remove unpin rlc clear_state_obj for gfx v8 when rlc init, which will make Stoney pm_suspend hang.

Signed-off-by: Likun Gao <Likun.Gao at amd.com>
---
 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 22 +++++++++++++++++++---
 1 file changed, 19 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
index d290718..0b73c6e 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
@@ -1292,6 +1292,8 @@ static int gfx_v8_0_cp_jump_table_num(struct amdgpu_device *adev)

 static int gfx_v8_0_rlc_init(struct amdgpu_device *adev)  {
+       volatile u32 *dst_ptr;
+       u32 dws;
        const struct cs_section_def *cs_data;
        int r;

@@ -1300,10 +1302,24 @@ static int gfx_v8_0_rlc_init(struct amdgpu_device *adev)
        cs_data = adev->gfx.rlc.cs_data;

        if (cs_data) {
-               /* init clear state block */
-               r = amdgpu_gfx_rlc_init_csb(adev);
-               if (r)
+               /* clear state block */
+               adev->gfx.rlc.clear_state_size = dws = adev->gfx.rlc.funcs->get_csb_size(adev);
+               r = amdgpu_bo_create_reserved(adev, dws * 4, PAGE_SIZE,
+                                             AMDGPU_GEM_DOMAIN_VRAM,
+                                             &adev->gfx.rlc.clear_state_obj,
+                                             &adev->gfx.rlc.clear_state_gpu_addr,
+                                             (void **)&adev->gfx.rlc.cs_ptr);
+               if (r) {
+                       dev_warn(adev->dev, "(%d) create RLC c bo failed\n", r);
+                       amdgpu_gfx_rlc_fini(adev);
                        return r;
+               }
+
+               /* set up the cs buffer */
+               dst_ptr = adev->gfx.rlc.cs_ptr;
+               adev->gfx.rlc.funcs->get_csb_buffer(adev, dst_ptr);
+               amdgpu_bo_kunmap(adev->gfx.rlc.clear_state_obj);
+               amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj);
        }

        if ((adev->asic_type == CHIP_CARRIZO) ||
--
2.7.4

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