[PATCH 10/36] drm/amd/display: Zero-out dsc init regs

Bhawanpreet Lakha Bhawanpreet.Lakha at amd.com
Mon Aug 19 14:34:49 UTC 2019

From: Nikola Cornij <nikola.cornij at amd.com>

Before a statically allocated PPS data structure, that did
get zeroed-out at startup, had been re-used for making packed PPS
SDP. With S3 fix, using a non-initialized PPS data structure was
introduced, while wrongly assuming it'd get initialized before it's
populated. As a consequence 'vbr_enable' and perhaps some other
fields are left uninitialized when making packed PPS SDP. This can
affect 'simple_422' as well because of the way PPS SDP packing is
done (the fields are not masked first, only shifted). The behavior
will be different, depending on the content of uninitialized data.

Zero-out PPS data structure at initialization time before it's

Fixes:  3b87378c604e929015385e5cc76d0bbd55c05347
	drm/amd/display: Set DSC before DIG front-end is connected to its back-end

Signed-off-by: Nikola Cornij <nikola.cornij at amd.com>
Reviewed-by: Wenjing Liu <Wenjing.Liu at amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha at amd.com>
 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c
index 379c9e4ac63b..c4f861e6bd53 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c
@@ -447,6 +447,8 @@ static void dsc_init_reg_values(struct dsc_reg_values *reg_vals)
 	int i;
+	memset(reg_vals, 0, sizeof(struct dsc_reg_values));
 	/* Non-PPS values */
 	reg_vals->dsc_clock_enable            = 1;
 	reg_vals->dsc_clock_gating_disable    = 0;

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