[PATCH] drm/amd/powerplay: add smu_map_helper function to unified map function
Wang, Kevin(Yang)
Kevin1.Wang at amd.com
Tue Aug 20 07:55:01 UTC 2019
1. add smu_map to replace old smu_11_0_cmn2aisc_mapping.
(next generation of smu ip also need this logic, eg: smu12 13 14...)
2. use smu_map_helper function to unified map code logic in smu
Signed-off-by: Kevin Wang <kevin1.wang at amd.com>
---
drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 19 ++++
drivers/gpu/drm/amd/powerplay/arcturus_ppt.c | 102 ++++--------------
.../gpu/drm/amd/powerplay/inc/amdgpu_smu.h | 7 ++
drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h | 15 +--
drivers/gpu/drm/amd/powerplay/navi10_ppt.c | 97 ++++-------------
drivers/gpu/drm/amd/powerplay/vega20_ppt.c | 96 ++++-------------
6 files changed, 86 insertions(+), 250 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
index 4df7fb6eaf3c..9e2a45ff23c4 100644
--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
@@ -56,6 +56,25 @@ const char *smu_get_feature_name(struct smu_context *smu, enum smu_feature_mask
return __smu_feature_names[feature];
}
+int smu_map_helper(struct smu_context *smu, struct smu_map *map_src,
+ uint32_t max_index, uint32_t index)
+{
+ struct smu_map *map = NULL;
+
+ if (!map_src)
+ return -EINVAL;
+
+ if (index >= max_index)
+ return -EINVAL;
+
+ map = &map_src[index];
+ if (!map->valid)
+ return -EINVAL;
+
+ return map->value;
+}
+
+
size_t smu_sys_get_pp_feature_mask(struct smu_context *smu, char *buf)
{
size_t size = 0;
diff --git a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
index 04a26072cf40..3416dcb5f40f 100644
--- a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
@@ -42,9 +42,9 @@
#define CTF_OFFSET_HBM 5
#define MSG_MAP(msg, index) \
- [SMU_MSG_##msg] = {1, (index)}
+ [SMU_MSG_##msg] = {true, (index)}
#define ARCTURUS_FEA_MAP(smu_feature, arcturus_feature) \
- [smu_feature] = {1, (arcturus_feature)}
+ [smu_feature] = {true, (arcturus_feature)}
#define SMU_FEATURES_LOW_MASK 0x00000000FFFFFFFF
#define SMU_FEATURES_LOW_SHIFT 0
@@ -63,7 +63,7 @@
/* possible frequency drift (1Mhz) */
#define EPSILON 1
-static struct smu_11_0_cmn2aisc_mapping arcturus_message_map[SMU_MSG_MAX_COUNT] = {
+static struct smu_map arcturus_message_map[SMU_MSG_MAX_COUNT] = {
MSG_MAP(TestMessage, PPSMC_MSG_TestMessage),
MSG_MAP(GetSmuVersion, PPSMC_MSG_GetSmuVersion),
MSG_MAP(GetDriverIfVersion, PPSMC_MSG_GetDriverIfVersion),
@@ -123,7 +123,7 @@ static struct smu_11_0_cmn2aisc_mapping arcturus_message_map[SMU_MSG_MAX_COUNT]
MSG_MAP(SetMemoryChannelEnable, PPSMC_MSG_SetMemoryChannelEnable),
};
-static struct smu_11_0_cmn2aisc_mapping arcturus_clk_map[SMU_CLK_COUNT] = {
+static struct smu_map arcturus_clk_map[SMU_CLK_COUNT] = {
CLK_MAP(GFXCLK, PPCLK_GFXCLK),
CLK_MAP(SCLK, PPCLK_GFXCLK),
CLK_MAP(SOCCLK, PPCLK_SOCCLK),
@@ -134,7 +134,7 @@ static struct smu_11_0_cmn2aisc_mapping arcturus_clk_map[SMU_CLK_COUNT] = {
CLK_MAP(VCLK, PPCLK_VCLK),
};
-static struct smu_11_0_cmn2aisc_mapping arcturus_feature_mask_map[SMU_FEATURE_COUNT] = {
+static struct smu_map arcturus_feature_mask_map[SMU_FEATURE_COUNT] = {
FEA_MAP(DPM_PREFETCHER),
FEA_MAP(DPM_GFXCLK),
FEA_MAP(DPM_UCLK),
@@ -161,7 +161,7 @@ static struct smu_11_0_cmn2aisc_mapping arcturus_feature_mask_map[SMU_FEATURE_CO
FEA_MAP(TEMP_DEPENDENT_VMIN),
};
-static struct smu_11_0_cmn2aisc_mapping arcturus_table_map[SMU_TABLE_COUNT] = {
+static struct smu_map arcturus_table_map[SMU_TABLE_COUNT] = {
TAB_MAP(PPTABLE),
TAB_MAP(AVFS),
TAB_MAP(AVFS_PSM_DEBUG),
@@ -172,12 +172,12 @@ static struct smu_11_0_cmn2aisc_mapping arcturus_table_map[SMU_TABLE_COUNT] = {
TAB_MAP(OVERDRIVE),
};
-static struct smu_11_0_cmn2aisc_mapping arcturus_pwr_src_map[SMU_POWER_SOURCE_COUNT] = {
+static struct smu_map arcturus_pwr_src_map[SMU_POWER_SOURCE_COUNT] = {
PWR_MAP(AC),
PWR_MAP(DC),
};
-static struct smu_11_0_cmn2aisc_mapping arcturus_workload_map[PP_SMC_POWER_PROFILE_COUNT] = {
+static struct smu_map arcturus_workload_map[PP_SMC_POWER_PROFILE_COUNT] = {
WORKLOAD_MAP(PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT, WORKLOAD_PPLIB_DEFAULT_BIT),
WORKLOAD_MAP(PP_SMC_POWER_PROFILE_POWERSAVING, WORKLOAD_PPLIB_POWER_SAVING_BIT),
WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VIDEO, WORKLOAD_PPLIB_VIDEO_BIT),
@@ -185,98 +185,34 @@ static struct smu_11_0_cmn2aisc_mapping arcturus_workload_map[PP_SMC_POWER_PROFI
WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CUSTOM, WORKLOAD_PPLIB_CUSTOM_BIT),
};
-static int arcturus_get_smu_msg_index(struct smu_context *smc, uint32_t index)
+static int arcturus_get_smu_msg_index(struct smu_context *smu, uint32_t index)
{
- struct smu_11_0_cmn2aisc_mapping mapping;
-
- if (index >= SMU_MSG_MAX_COUNT)
- return -EINVAL;
-
- mapping = arcturus_message_map[index];
- if (!(mapping.valid_mapping))
- return -EINVAL;
-
- return mapping.map_to;
+ return smu_map_helper(smu, arcturus_message_map, SMU_MSG_MAX_COUNT, index);
}
-static int arcturus_get_smu_clk_index(struct smu_context *smc, uint32_t index)
+static int arcturus_get_smu_clk_index(struct smu_context *smu, uint32_t index)
{
- struct smu_11_0_cmn2aisc_mapping mapping;
-
- if (index >= SMU_CLK_COUNT)
- return -EINVAL;
-
- mapping = arcturus_clk_map[index];
- if (!(mapping.valid_mapping)) {
- pr_warn("Unsupported SMU clk: %d\n", index);
- return -EINVAL;
- }
-
- return mapping.map_to;
+ return smu_map_helper(smu, arcturus_clk_map, SMU_CLK_COUNT, index);
}
-static int arcturus_get_smu_feature_index(struct smu_context *smc, uint32_t index)
+static int arcturus_get_smu_feature_index(struct smu_context *smu, uint32_t index)
{
- struct smu_11_0_cmn2aisc_mapping mapping;
-
- if (index >= SMU_FEATURE_COUNT)
- return -EINVAL;
-
- mapping = arcturus_feature_mask_map[index];
- if (!(mapping.valid_mapping)) {
- return -EINVAL;
- }
-
- return mapping.map_to;
+ return smu_map_helper(smu, arcturus_feature_mask_map, SMU_FEATURE_COUNT, index);
}
-static int arcturus_get_smu_table_index(struct smu_context *smc, uint32_t index)
+static int arcturus_get_smu_table_index(struct smu_context *smu, uint32_t index)
{
- struct smu_11_0_cmn2aisc_mapping mapping;
-
- if (index >= SMU_TABLE_COUNT)
- return -EINVAL;
-
- mapping = arcturus_table_map[index];
- if (!(mapping.valid_mapping)) {
- pr_warn("Unsupported SMU table: %d\n", index);
- return -EINVAL;
- }
-
- return mapping.map_to;
+ return smu_map_helper(smu, arcturus_table_map, SMU_TABLE_COUNT, index);
}
-static int arcturus_get_pwr_src_index(struct smu_context *smc, uint32_t index)
+static int arcturus_get_pwr_src_index(struct smu_context *smu, uint32_t index)
{
- struct smu_11_0_cmn2aisc_mapping mapping;
-
- if (index >= SMU_POWER_SOURCE_COUNT)
- return -EINVAL;
-
- mapping = arcturus_pwr_src_map[index];
- if (!(mapping.valid_mapping)) {
- pr_warn("Unsupported SMU power source: %d\n", index);
- return -EINVAL;
- }
-
- return mapping.map_to;
+ return smu_map_helper(smu, arcturus_pwr_src_map, SMU_POWER_SOURCE_COUNT, index);
}
-
static int arcturus_get_workload_type(struct smu_context *smu, enum PP_SMC_POWER_PROFILE profile)
{
- struct smu_11_0_cmn2aisc_mapping mapping;
-
- if (profile > PP_SMC_POWER_PROFILE_CUSTOM)
- return -EINVAL;
-
- mapping = arcturus_workload_map[profile];
- if (!(mapping.valid_mapping)) {
- pr_warn("Unsupported SMU power source: %d\n", profile);
- return -EINVAL;
- }
-
- return mapping.map_to;
+ return smu_map_helper(smu, arcturus_workload_map, PP_SMC_POWER_PROFILE_COUNT, (uint32_t)profile);
}
static int arcturus_tables_init(struct smu_context *smu, struct smu_table *tables)
diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
index fc59d9686e61..6404ad5249d4 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
@@ -206,6 +206,11 @@ struct smu_clock_info {
uint32_t max_bus_bandwidth;
};
+struct smu_map {
+ bool valid;
+ int value;
+};
+
struct smu_bios_boot_up_values
{
uint32_t revision;
@@ -809,5 +814,7 @@ const char *smu_get_message_name(struct smu_context *smu, enum smu_message_type
const char *smu_get_feature_name(struct smu_context *smu, enum smu_feature_mask feature);
size_t smu_sys_get_pp_feature_mask(struct smu_context *smu, char *buf);
int smu_sys_set_pp_feature_mask(struct smu_context *smu, uint64_t new_mask);
+int smu_map_helper(struct smu_context *smu, struct smu_map *map_src,
+ uint32_t max_index, uint32_t index);
#endif
diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h b/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
index acbb83d179be..ef59850b3fef 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
@@ -49,24 +49,19 @@
#define SMU11_TOOL_SIZE 0x19000
#define CLK_MAP(clk, index) \
- [SMU_##clk] = {1, (index)}
+ [SMU_##clk] = {true, (index)}
#define FEA_MAP(fea) \
- [SMU_FEATURE_##fea##_BIT] = {1, FEATURE_##fea##_BIT}
+ [SMU_FEATURE_##fea##_BIT] = {true, FEATURE_##fea##_BIT}
#define TAB_MAP(tab) \
- [SMU_TABLE_##tab] = {1, TABLE_##tab}
+ [SMU_TABLE_##tab] = {true, TABLE_##tab}
#define PWR_MAP(tab) \
- [SMU_POWER_SOURCE_##tab] = {1, POWER_SOURCE_##tab}
+ [SMU_POWER_SOURCE_##tab] = {true, POWER_SOURCE_##tab}
#define WORKLOAD_MAP(profile, workload) \
- [profile] = {1, (workload)}
-
-struct smu_11_0_cmn2aisc_mapping {
- int valid_mapping;
- int map_to;
-};
+ [profile] = {true, (workload)}
struct smu_11_0_max_sustainable_clocks {
uint32_t display_clock;
diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
index 920156e9fb9d..9838beecec2e 100644
--- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
@@ -49,9 +49,9 @@
FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT))
#define MSG_MAP(msg, index) \
- [SMU_MSG_##msg] = {1, (index)}
+ [SMU_MSG_##msg] = {true, (index)}
-static struct smu_11_0_cmn2aisc_mapping navi10_message_map[SMU_MSG_MAX_COUNT] = {
+static struct smu_map navi10_message_map[SMU_MSG_MAX_COUNT] = {
MSG_MAP(TestMessage, PPSMC_MSG_TestMessage),
MSG_MAP(GetSmuVersion, PPSMC_MSG_GetSmuVersion),
MSG_MAP(GetDriverIfVersion, PPSMC_MSG_GetDriverIfVersion),
@@ -118,7 +118,7 @@ static struct smu_11_0_cmn2aisc_mapping navi10_message_map[SMU_MSG_MAX_COUNT] =
MSG_MAP(ArmD3, PPSMC_MSG_ArmD3),
};
-static struct smu_11_0_cmn2aisc_mapping navi10_clk_map[SMU_CLK_COUNT] = {
+static struct smu_map navi10_clk_map[SMU_CLK_COUNT] = {
CLK_MAP(GFXCLK, PPCLK_GFXCLK),
CLK_MAP(SCLK, PPCLK_GFXCLK),
CLK_MAP(SOCCLK, PPCLK_SOCCLK),
@@ -133,7 +133,7 @@ static struct smu_11_0_cmn2aisc_mapping navi10_clk_map[SMU_CLK_COUNT] = {
CLK_MAP(PHYCLK, PPCLK_PHYCLK),
};
-static struct smu_11_0_cmn2aisc_mapping navi10_feature_mask_map[SMU_FEATURE_COUNT] = {
+static struct smu_map navi10_feature_mask_map[SMU_FEATURE_COUNT] = {
FEA_MAP(DPM_PREFETCHER),
FEA_MAP(DPM_GFXCLK),
FEA_MAP(DPM_GFX_PACE),
@@ -178,7 +178,7 @@ static struct smu_11_0_cmn2aisc_mapping navi10_feature_mask_map[SMU_FEATURE_COUN
FEA_MAP(ATHUB_PG),
};
-static struct smu_11_0_cmn2aisc_mapping navi10_table_map[SMU_TABLE_COUNT] = {
+static struct smu_map navi10_table_map[SMU_TABLE_COUNT] = {
TAB_MAP(PPTABLE),
TAB_MAP(WATERMARKS),
TAB_MAP(AVFS),
@@ -193,12 +193,12 @@ static struct smu_11_0_cmn2aisc_mapping navi10_table_map[SMU_TABLE_COUNT] = {
TAB_MAP(PACE),
};
-static struct smu_11_0_cmn2aisc_mapping navi10_pwr_src_map[SMU_POWER_SOURCE_COUNT] = {
+static struct smu_map navi10_pwr_src_map[SMU_POWER_SOURCE_COUNT] = {
PWR_MAP(AC),
PWR_MAP(DC),
};
-static struct smu_11_0_cmn2aisc_mapping navi10_workload_map[PP_SMC_POWER_PROFILE_COUNT] = {
+static struct smu_map navi10_workload_map[PP_SMC_POWER_PROFILE_COUNT] = {
WORKLOAD_MAP(PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT, WORKLOAD_PPLIB_DEFAULT_BIT),
WORKLOAD_MAP(PP_SMC_POWER_PROFILE_FULLSCREEN3D, WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT),
WORKLOAD_MAP(PP_SMC_POWER_PROFILE_POWERSAVING, WORKLOAD_PPLIB_POWER_SAVING_BIT),
@@ -208,95 +208,34 @@ static struct smu_11_0_cmn2aisc_mapping navi10_workload_map[PP_SMC_POWER_PROFILE
WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CUSTOM, WORKLOAD_PPLIB_CUSTOM_BIT),
};
-static int navi10_get_smu_msg_index(struct smu_context *smc, uint32_t index)
+static int navi10_get_smu_msg_index(struct smu_context *smu, uint32_t index)
{
- struct smu_11_0_cmn2aisc_mapping mapping;
-
- if (index > SMU_MSG_MAX_COUNT)
- return -EINVAL;
-
- mapping = navi10_message_map[index];
- if (!(mapping.valid_mapping)) {
- return -EINVAL;
- }
-
- return mapping.map_to;
+ return smu_map_helper(smu, navi10_message_map, SMU_MSG_MAX_COUNT, index);
}
-static int navi10_get_smu_clk_index(struct smu_context *smc, uint32_t index)
+static int navi10_get_smu_clk_index(struct smu_context *smu, uint32_t index)
{
- struct smu_11_0_cmn2aisc_mapping mapping;
-
- if (index >= SMU_CLK_COUNT)
- return -EINVAL;
-
- mapping = navi10_clk_map[index];
- if (!(mapping.valid_mapping)) {
- return -EINVAL;
- }
-
- return mapping.map_to;
+ return smu_map_helper(smu, navi10_clk_map, SMU_CLK_COUNT, index);
}
-static int navi10_get_smu_feature_index(struct smu_context *smc, uint32_t index)
+static int navi10_get_smu_feature_index(struct smu_context *smu, uint32_t index)
{
- struct smu_11_0_cmn2aisc_mapping mapping;
-
- if (index >= SMU_FEATURE_COUNT)
- return -EINVAL;
-
- mapping = navi10_feature_mask_map[index];
- if (!(mapping.valid_mapping)) {
- return -EINVAL;
- }
-
- return mapping.map_to;
+ return smu_map_helper(smu, navi10_feature_mask_map, SMU_FEATURE_COUNT, index);
}
-static int navi10_get_smu_table_index(struct smu_context *smc, uint32_t index)
+static int navi10_get_smu_table_index(struct smu_context *smu, uint32_t index)
{
- struct smu_11_0_cmn2aisc_mapping mapping;
-
- if (index >= SMU_TABLE_COUNT)
- return -EINVAL;
-
- mapping = navi10_table_map[index];
- if (!(mapping.valid_mapping)) {
- return -EINVAL;
- }
-
- return mapping.map_to;
+ return smu_map_helper(smu, navi10_table_map, SMU_TABLE_COUNT, index);
}
-static int navi10_get_pwr_src_index(struct smu_context *smc, uint32_t index)
+static int navi10_get_pwr_src_index(struct smu_context *smu, uint32_t index)
{
- struct smu_11_0_cmn2aisc_mapping mapping;
-
- if (index >= SMU_POWER_SOURCE_COUNT)
- return -EINVAL;
-
- mapping = navi10_pwr_src_map[index];
- if (!(mapping.valid_mapping)) {
- return -EINVAL;
- }
-
- return mapping.map_to;
+ return smu_map_helper(smu, navi10_pwr_src_map, SMU_POWER_SOURCE_COUNT, index);
}
-
static int navi10_get_workload_type(struct smu_context *smu, enum PP_SMC_POWER_PROFILE profile)
{
- struct smu_11_0_cmn2aisc_mapping mapping;
-
- if (profile > PP_SMC_POWER_PROFILE_CUSTOM)
- return -EINVAL;
-
- mapping = navi10_workload_map[profile];
- if (!(mapping.valid_mapping)) {
- return -EINVAL;
- }
-
- return mapping.map_to;
+ return smu_map_helper(smu, navi10_workload_map, PP_SMC_POWER_PROFILE_COUNT, (uint32_t)profile);
}
static bool is_asic_secure(struct smu_context *smu)
diff --git a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
index acf075393c13..6162be25b6d2 100644
--- a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
@@ -47,7 +47,7 @@
#define CTF_OFFSET_HBM 5
#define MSG_MAP(msg) \
- [SMU_MSG_##msg] = {1, PPSMC_MSG_##msg}
+ [SMU_MSG_##msg] = {true, PPSMC_MSG_##msg}
#define SMC_DPM_FEATURE (FEATURE_DPM_PREFETCHER_MASK | \
FEATURE_DPM_GFXCLK_MASK | \
@@ -59,7 +59,7 @@
FEATURE_DPM_LINK_MASK | \
FEATURE_DPM_DCEFCLK_MASK)
-static struct smu_11_0_cmn2aisc_mapping vega20_message_map[SMU_MSG_MAX_COUNT] = {
+static struct smu_map vega20_message_map[SMU_MSG_MAX_COUNT] = {
MSG_MAP(TestMessage),
MSG_MAP(GetSmuVersion),
MSG_MAP(GetDriverIfVersion),
@@ -145,7 +145,7 @@ static struct smu_11_0_cmn2aisc_mapping vega20_message_map[SMU_MSG_MAX_COUNT] =
MSG_MAP(GetAVFSVoltageByDpm),
};
-static struct smu_11_0_cmn2aisc_mapping vega20_clk_map[SMU_CLK_COUNT] = {
+static struct smu_map vega20_clk_map[SMU_CLK_COUNT] = {
CLK_MAP(GFXCLK, PPCLK_GFXCLK),
CLK_MAP(VCLK, PPCLK_VCLK),
CLK_MAP(DCLK, PPCLK_DCLK),
@@ -159,7 +159,7 @@ static struct smu_11_0_cmn2aisc_mapping vega20_clk_map[SMU_CLK_COUNT] = {
CLK_MAP(FCLK, PPCLK_FCLK),
};
-static struct smu_11_0_cmn2aisc_mapping vega20_feature_mask_map[SMU_FEATURE_COUNT] = {
+static struct smu_map vega20_feature_mask_map[SMU_FEATURE_COUNT] = {
FEA_MAP(DPM_PREFETCHER),
FEA_MAP(DPM_GFXCLK),
FEA_MAP(DPM_UCLK),
@@ -195,7 +195,7 @@ static struct smu_11_0_cmn2aisc_mapping vega20_feature_mask_map[SMU_FEATURE_COUN
FEA_MAP(XGMI),
};
-static struct smu_11_0_cmn2aisc_mapping vega20_table_map[SMU_TABLE_COUNT] = {
+static struct smu_map vega20_table_map[SMU_TABLE_COUNT] = {
TAB_MAP(PPTABLE),
TAB_MAP(WATERMARKS),
TAB_MAP(AVFS),
@@ -208,12 +208,12 @@ static struct smu_11_0_cmn2aisc_mapping vega20_table_map[SMU_TABLE_COUNT] = {
TAB_MAP(OVERDRIVE),
};
-static struct smu_11_0_cmn2aisc_mapping vega20_pwr_src_map[SMU_POWER_SOURCE_COUNT] = {
+static struct smu_map vega20_pwr_src_map[SMU_POWER_SOURCE_COUNT] = {
PWR_MAP(AC),
PWR_MAP(DC),
};
-static struct smu_11_0_cmn2aisc_mapping vega20_workload_map[PP_SMC_POWER_PROFILE_COUNT] = {
+static struct smu_map vega20_workload_map[PP_SMC_POWER_PROFILE_COUNT] = {
WORKLOAD_MAP(PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT, WORKLOAD_DEFAULT_BIT),
WORKLOAD_MAP(PP_SMC_POWER_PROFILE_FULLSCREEN3D, WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT),
WORKLOAD_MAP(PP_SMC_POWER_PROFILE_POWERSAVING, WORKLOAD_PPLIB_POWER_SAVING_BIT),
@@ -223,94 +223,34 @@ static struct smu_11_0_cmn2aisc_mapping vega20_workload_map[PP_SMC_POWER_PROFILE
WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CUSTOM, WORKLOAD_PPLIB_CUSTOM_BIT),
};
-static int vega20_get_smu_table_index(struct smu_context *smc, uint32_t index)
+static int vega20_get_smu_table_index(struct smu_context *smu, uint32_t index)
{
- struct smu_11_0_cmn2aisc_mapping mapping;
-
- if (index >= SMU_TABLE_COUNT)
- return -EINVAL;
-
- mapping = vega20_table_map[index];
- if (!(mapping.valid_mapping)) {
- return -EINVAL;
- }
-
- return mapping.map_to;
+ return smu_map_helper(smu, vega20_table_map, SMU_TABLE_COUNT, index);
}
-static int vega20_get_pwr_src_index(struct smu_context *smc, uint32_t index)
+static int vega20_get_pwr_src_index(struct smu_context *smu, uint32_t index)
{
- struct smu_11_0_cmn2aisc_mapping mapping;
-
- if (index >= SMU_POWER_SOURCE_COUNT)
- return -EINVAL;
-
- mapping = vega20_pwr_src_map[index];
- if (!(mapping.valid_mapping)) {
- return -EINVAL;
- }
-
- return mapping.map_to;
+ return smu_map_helper(smu, vega20_pwr_src_map, SMU_POWER_SOURCE_COUNT, index);
}
-static int vega20_get_smu_feature_index(struct smu_context *smc, uint32_t index)
+static int vega20_get_smu_feature_index(struct smu_context *smu, uint32_t index)
{
- struct smu_11_0_cmn2aisc_mapping mapping;
-
- if (index >= SMU_FEATURE_COUNT)
- return -EINVAL;
-
- mapping = vega20_feature_mask_map[index];
- if (!(mapping.valid_mapping)) {
- return -EINVAL;
- }
-
- return mapping.map_to;
+ return smu_map_helper(smu, vega20_feature_mask_map, SMU_FEATURE_COUNT, index);
}
-static int vega20_get_smu_clk_index(struct smu_context *smc, uint32_t index)
+static int vega20_get_smu_clk_index(struct smu_context *smu, uint32_t index)
{
- struct smu_11_0_cmn2aisc_mapping mapping;
-
- if (index >= SMU_CLK_COUNT)
- return -EINVAL;
-
- mapping = vega20_clk_map[index];
- if (!(mapping.valid_mapping)) {
- return -EINVAL;
- }
-
- return mapping.map_to;
+ return smu_map_helper(smu, vega20_clk_map, SMU_CLK_COUNT, index);
}
-static int vega20_get_smu_msg_index(struct smu_context *smc, uint32_t index)
+static int vega20_get_smu_msg_index(struct smu_context *smu, uint32_t index)
{
- struct smu_11_0_cmn2aisc_mapping mapping;
-
- if (index >= SMU_MSG_MAX_COUNT)
- return -EINVAL;
-
- mapping = vega20_message_map[index];
- if (!(mapping.valid_mapping)) {
- return -EINVAL;
- }
-
- return mapping.map_to;
+ return smu_map_helper(smu, vega20_message_map, SMU_MSG_MAX_COUNT, index);
}
static int vega20_get_workload_type(struct smu_context *smu, enum PP_SMC_POWER_PROFILE profile)
{
- struct smu_11_0_cmn2aisc_mapping mapping;
-
- if (profile > PP_SMC_POWER_PROFILE_CUSTOM)
- return -EINVAL;
-
- mapping = vega20_workload_map[profile];
- if (!(mapping.valid_mapping)) {
- return -EINVAL;
- }
-
- return mapping.map_to;
+ return smu_map_helper(smu, vega20_workload_map, PP_SMC_POWER_PROFILE_COUNT, (uint32_t)profile);
}
static int vega20_tables_init(struct smu_context *smu, struct smu_table *tables)
--
2.22.0
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