[PATCH v2 00/14] Display Stream Compression (DSC) for AMD Navi

David Francis David.Francis at amd.com
Tue Aug 20 19:11:49 UTC 2019

This patchset enables Display Stream Compression (DSC) on DP
connectors on Navi ASICs, both SST and DSC.

8k60 and 4k144 support requires ODM combine, an AMD internal
feature that may be a bit buggy right now.

Patches 1 through 5 enable DSC for SST. Most of the work was
already done in the Navi promotion patches; this just hooks
it up to the atomic interface. The first two reverts are of temporary
changes to block off DSC. The third is of a commit that was
accidentally promoted twice. The fourth and last revert fixes a
potential issue with ODM combine.

Patches 6 and 7 are fixes for bugs that would be exposed by
MST DSC. One fix is with the MST code and the other in the DSC code.

Patches 8, 9, and 10 are small DRM changes required for DSC MST:
FEC, a new bit in the standard; some export definitions; and
a previously uninitialized variable.

Patches 11 through 14 are the DSC MST policy itself. This includes
the code for detecting and validating DSC capabilities, enabling
DSC over a link, computing the fair DSC configurations for
multiple DSC displays, and adding to atomic state crtcs that might
need reprogramming due to DSC.

v2: Updating patches 6 and 14 in respoinse to Nick's feedback

David Francis (14):
  Revert "drm/amd/display: skip dsc config for navi10 bring up"
  Revert "drm/amd/display: navi10 bring up skip dsc encoder config"
  Revert "drm/amd/display: add global master update lock for DCN2"
  Revert "drm/amd/display: Fix underscan not using proper scaling"
  drm/amd/display: Enable SST DSC in DM
  drm/dp-mst: Use dc and drm helpers to compute timeslots
  drm/amd/display: Initialize DSC PPS variables to 0
  drm/dp-mst: Parse FEC capability on MST ports
  drm/dp-mst: Export symbols for dpcd read/write
  drm/dp-mst: Fill branch->num_ports
  drm/amd/display: Validate DSC caps on MST endpoints
  drm/amd/display: Write DSC enable to MST DPCD
  drm/amd/display: MST DSC compute fair share
  drm/amd/display: Trigger modesets on MST DSC connectors

 .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 110 +++-
 .../amd/display/amdgpu_dm/amdgpu_dm_helpers.c |  48 +-
 .../display/amdgpu_dm/amdgpu_dm_mst_types.c   | 498 +++++++++++++++++-
 .../display/amdgpu_dm/amdgpu_dm_mst_types.h   |   5 +
 drivers/gpu/drm/amd/display/dc/core/dc.c      |  12 +-
 .../drm/amd/display/dc/core/dc_link_hwss.c    |   3 +
 .../gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c  |   3 +
 .../drm/amd/display/dc/dcn20/dcn20_hwseq.c    |   4 -
 .../gpu/drm/amd/display/dc/dcn20/dcn20_optc.c |  72 +--
 .../gpu/drm/amd/display/dc/dcn20/dcn20_optc.h |   3 -
 .../drm/amd/display/dc/dcn20/dcn20_resource.c |   7 +-
 .../drm/amd/display/dc/dcn20/dcn20_resource.h |   1 +
 .../display/dc/dcn20/dcn20_stream_encoder.c   |   8 -
 .../amd/display/dc/inc/hw/timing_generator.h  |   2 -
 drivers/gpu/drm/drm_dp_mst_topology.c         |  47 ++
 include/drm/drm_dp_mst_helper.h               |   5 +-
 16 files changed, 708 insertions(+), 120 deletions(-)


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