[PATCH] drm/amdgpu/sdma5: fix number of sdma5 trap irq types for navi1x

[Yuan, Xiaojie]

Thanks Alex. I've sent out patch v2.

BR,
Xiaojie

> On Aug 21, 2019, at 9:30 PM, Alex Deucher <alexdeucher at gmail.com> wrote:
> 
>> On Wed, Aug 21, 2019 at 9:23 AM Yuan, Xiaojie <Xiaojie.Yuan at amd.com> wrote:
>> 
>> navi1x has 2 sdma engines but commit
>> "e7b58d03b678 drm/amdgpu: reorganize sdma v4 code to support more instances"
>> changes the max number of sdma irq types (AMDGPU_SDMA_IRQ_LAST) from 2 to 8
>> which causes amdgpu_irq_gpu_reset_resume_helper() to recover irq of sdma
>> engines with following logic:
>> 
>> (enable irq for sdma0) * 1 time
>> (enable irq for sdma1) * 1 time
>> (disable irq for sdma1) * 6 times
>> 
>> as a result, after gpu reset, interrupt for sdma1 is lost.
>> 
>> for asics with more sdma5 engines, we need to set 'num_types' depending
>> on asic type just like what sdma_v4_0_set_irq_funcs() does.
>> 
>> Signed-off-by: Xiaojie Yuan <xiaojie.yuan at amd.com>
>> ---
>> drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c | 2 +-
>> 1 file changed, 1 insertion(+), 1 deletion(-)
>> 
>> diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
>> index 41932d8b88c3..32bce3eb5fc2 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
>> @@ -1625,7 +1625,7 @@ static const struct amdgpu_irq_src_funcs sdma_v5_0_illegal_inst_irq_funcs = {
>> 
>> static void sdma_v5_0_set_irq_funcs(struct amdgpu_device *adev)
>> {
>> -       adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_LAST;
>> +       adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_INSTANCE2;
> 
> It would be more future proof to set the num_types based on the num instances.
> 
> Alex
> 
>>        adev->sdma.trap_irq.funcs = &sdma_v5_0_trap_irq_funcs;
>>        adev->sdma.illegal_inst_irq.funcs = &sdma_v5_0_illegal_inst_irq_funcs;
>> }
>> --
>> 2.20.1
>> 
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