[PATCH v3 00/16] Display Stream Compression (DSC) for AMD Navi

[Lyude Paul]

What branch does this patch series actually apply to? I've been trying to
apply this locally, but it doesn't appear to apply against drm-tip/drm-tip,
amdgpu-next/drm-next, or origin (e.g. kernel.org) /master. Is there any chance
we could have this go against drm-tip instead (and even better, split out the
DRM-specific bits into their own patch series?)

On Wed, 2019-08-21 at 16:01 -0400, David Francis wrote:
> This patchset enables Display Stream Compression (DSC) on DP
> connectors on Navi ASICs, both SST and DSC.
> 
> 8k60 and 4k144 support requires ODM combine, an AMD internal
> feature that may be a bit buggy right now.
> 
> Patches 1 through 5 enable DSC for SST. Most of the work was
> already done in the Navi promotion patches; this just hooks
> it up to the atomic interface. The first two reverts are of temporary
> changes to block off DSC. The third is of a commit that was
> accidentally promoted twice. The fourth and last revert fixes a
> potential issue with ODM combine.
> 
> Patches 6, 7 and 8 are fixes for bugs that would be exposed by
> MST DSC. Patches 6 and 7 add and use a new DRM helper for MST
> calculations. Patch 8 fixes a silly use-uninitialized
> 
> Patches 9, 10, and 11 are small DRM changes required for DSC MST:
> FEC, a new bit in the standard; MST DPCD from drivers; and
> a previously uninitialized variable.
> 
> Patches 12 through 16 are the DSC MST policy itself. Patch 12
> adds DSC aux access helpers to DRM, and patches 13 and 14 make
> use of those helpers. Patch 15 deals with dividing bandwidth
> fairly between multiple streams, and patch 16 ensures
> that MST CRTC that may change DSC config are reprogrammed
> 
> v2: Updating patches 6 and 14 in respoinse to Nick's feedback
> v3: Add return value to patch 6 and split it (now patches 6 & 7)
>     New patch 10 adding MST DPCD read/write support
>     Minor fix (num_ports--) to patch 11
>     Add DRM helpers (patch 12)
> 
> David Francis (16):
>   Revert "drm/amd/display: skip dsc config for navi10 bring up"
>   Revert "drm/amd/display: navi10 bring up skip dsc encoder config"
>   Revert "drm/amd/display: add global master update lock for DCN2"
>   Revert "drm/amd/display: Fix underscan not using proper scaling"
>   drm/amd/display: Enable SST DSC in DM
>   drm/dp-mst: Add PBN calculation for DSC modes
>   drm/amd/display: Use correct helpers to compute timeslots
>   drm/amd/display: Initialize DSC PPS variables to 0
>   drm/dp-mst: Parse FEC capability on MST ports
>   drm/dp-mst: Add MST support to DP DPCD R/W functions
>   drm/dp-mst: Fill branch->num_ports
>   drm/dp-mst: Add helpers for querying and enabling MST DSC
>   drm/amd/display: Validate DSC caps on MST endpoints
>   drm/amd/display: Write DSC enable to MST DPCD
>   drm/amd/display: MST DSC compute fair share
>   drm/amd/display: Trigger modesets on MST DSC connectors
> 
>  .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 113 ++++-
>  .../amd/display/amdgpu_dm/amdgpu_dm_helpers.c |  33 +-
>  .../display/amdgpu_dm/amdgpu_dm_mst_types.c   | 402 +++++++++++++++++-
>  .../display/amdgpu_dm/amdgpu_dm_mst_types.h   |   4 +
>  drivers/gpu/drm/amd/display/dc/core/dc.c      |  12 +-
>  .../drm/amd/display/dc/core/dc_link_hwss.c    |   3 +
>  .../gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c  |   3 +
>  .../drm/amd/display/dc/dcn20/dcn20_hwseq.c    |   4 -
>  .../gpu/drm/amd/display/dc/dcn20/dcn20_optc.c |  72 +---
>  .../gpu/drm/amd/display/dc/dcn20/dcn20_optc.h |   3 -
>  .../drm/amd/display/dc/dcn20/dcn20_resource.c |   7 +-
>  .../drm/amd/display/dc/dcn20/dcn20_resource.h |   1 +
>  .../display/dc/dcn20/dcn20_stream_encoder.c   |   8 -
>  .../amd/display/dc/inc/hw/timing_generator.h  |   2 -
>  drivers/gpu/drm/drm_dp_aux_dev.c              |  12 +-
>  drivers/gpu/drm/drm_dp_helper.c               |  10 +-
>  drivers/gpu/drm/drm_dp_mst_topology.c         | 240 +++++++++++
>  include/drm/drm_dp_mst_helper.h               |   8 +-
>  18 files changed, 806 insertions(+), 131 deletions(-)
> 
-- 
Cheers,
	Lyude Paul