[RFC] AMD polaris MEM_AP_SIZE location (PCI BAR aperture size)

[Petr Cvek]

Dne 28. 08. 19 v 10:31 Christian König napsal(a):
> Hi Petr,
> 
> well that is indeed a rather unusual use case.
> 
> I'm not 100% sure how you actually hacked the HD4550 to do what you want to do, cause this ASIC generation shouldn't support this.

I don't remember correctly how exactly I've managed to do that but I think the process was: 

I compared different BIOSes first and I found a correlation between aperture sizes in the ROM images of older (x1300/R520) generation. While doing that I've found mentions of MEM_AP_SIZE ROM powerup strap registers (from x.org documents) and I tried to flash the settings of HD4550 from 256MB (default) directly to 64MB and I was surprised it worked (I've though it will be only 128MB). IF I google the "MEM_AP_SIZE" now I can find a document [1], which says (page 56) the ROM address is 0x78 (page 56) and the table says 64MB is possible, which both match the experiment.

Of course the bios is now CRC broken, but it doesn't matter in linux (the ROM code is just x86 anyway).

[1] https://dev.xdevs.com/attachments/download/233/AMD_RV710_ds_nda_1.01b.pdf

> 
> For a Polaris you can just use the PCIe resizeable BAR extension. For how to use it see the pci_resize_resource() function in the linux kernel.
> 
> Please be aware that we usually use the function to increase the BAR size to allow the CPU to access more of the on board memory, so making it smaller might actually not be tested at all.

Yeah but sadly it seems it is possible to only increase the BAR size from its currently default 256MB.

> 
> Regards,
> Christian.
> 
> 
> Am 27.08.19 um 04:36 schrieb Petr Cvek:
>> Hello,
>>
>> I'm trying to run AMD GPUs in unusual configurations. I was able to decrease the PCI BAR size in HD4550 by its BIOS strap configuration and change it to 64MB (and I was able to run it on MIPS vocore2 board :-D ). Is there a similar configuration location for AMD polaris 11/RX 460 BIOS?
>>
>> Petr Cvek
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>