[PATCH 00/23] Add DC support for Renoir
Alex Deucher
alexdeucher at gmail.com
Wed Aug 28 19:56:00 UTC 2019
This patch set adds initial DC display support for
Renoir. Renoir is a new APU.
I have omitted the register patch due to size. The
full tree is available here:
https://cgit.freedesktop.org/~agd5f/linux/log/?h=amd-staging-drm-next-renoir-dc
Bhawanpreet Lakha (20):
drm/amd/display: Add Renoir registers (v3)
drm/amd/display: Add Renoir clock registers list
drm/amd/display: Add Renoir hw_seq register list
drm/amd/display: Add pp_smu functions for Renoir
drm/amd/display: Add Renoir irq_services
drm/amd/display: Add hubp block for Renoir (v2)
drm/amd/display: Add Renoir hubbub registers list
drm/amd/display: Add Renoir Hubbub (v2)
drm/amd/display: Add Renoir clock manager
drm/amd/display: Add Renoir resource (v2)
drm/amd/display: Add Renoir GPIO
drm/amd/display: Add Renoir DML
drm/amd/display: Fix register names
drm/amd/display: Handle Renoir in DC
drm/amd/display: Handle Renoir in amdgpu_dm (v2)
drm/amd/display: call update_bw_bounding_box
drm/amd/display: add dal_asic_id for renoir
drm/amd/display: add dcn21 core DC changes
drm/amd/display: build dcn21 blocks
drm/amd/display: add Renoir to kconfig
Roman Li (3):
drm/amd/display: Correct order of RV family clk managers for Renoir
drm/amd/display: Add DCN2.1 changes to DML
drm/amdgpu: Enable DC on Renoir
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 3 +
drivers/gpu/drm/amd/amdgpu/soc15.c | 6 +
drivers/gpu/drm/amd/display/Kconfig | 8 +
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 14 +
drivers/gpu/drm/amd/display/dc/Makefile | 3 +
.../display/dc/bios/command_table_helper2.c | 5 +
.../gpu/drm/amd/display/dc/clk_mgr/Makefile | 10 +
.../gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c | 9 +
.../amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c | 590 +
.../amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.h | 39 +
.../dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c | 200 +
.../dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.h | 40 +
drivers/gpu/drm/amd/display/dc/core/dc.c | 5 +
.../gpu/drm/amd/display/dc/core/dc_resource.c | 12 +
drivers/gpu/drm/amd/display/dc/dc.h | 3 +
.../drm/amd/display/dc/dce/dce_clock_source.h | 17 +
.../gpu/drm/amd/display/dc/dce/dce_hwseq.h | 97 +
.../drm/amd/display/dc/dcn10/dcn10_hubbub.h | 73 +
.../drm/amd/display/dc/dcn20/dcn20_hubbub.h | 10 +
.../gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h | 35 +
drivers/gpu/drm/amd/display/dc/dcn21/Makefile | 10 +
.../drm/amd/display/dc/dcn21/dcn21_hubbub.c | 595 +
.../drm/amd/display/dc/dcn21/dcn21_hubbub.h | 132 +
.../gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c | 244 +
.../gpu/drm/amd/display/dc/dcn21/dcn21_hubp.h | 133 +
.../drm/amd/display/dc/dcn21/dcn21_resource.c | 1680 +
.../drm/amd/display/dc/dcn21/dcn21_resource.h | 45 +
drivers/gpu/drm/amd/display/dc/dm_pp_smu.h | 47 +
drivers/gpu/drm/amd/display/dc/dml/Makefile | 8 +
.../dc/dml/dcn21/display_mode_vba_21.c | 6123 ++
.../dc/dml/dcn21/display_mode_vba_21.h | 32 +
.../dc/dml/dcn21/display_rq_dlg_calc_21.c | 1823 +
.../dc/dml/dcn21/display_rq_dlg_calc_21.h | 73 +
.../drm/amd/display/dc/dml/display_mode_lib.c | 19 +
.../drm/amd/display/dc/dml/display_mode_lib.h | 3 +
drivers/gpu/drm/amd/display/dc/gpio/Makefile | 7 +
.../display/dc/gpio/dcn21/hw_factory_dcn21.c | 210 +
.../display/dc/gpio/dcn21/hw_factory_dcn21.h | 33 +
.../dc/gpio/dcn21/hw_translate_dcn21.c | 386 +
.../dc/gpio/dcn21/hw_translate_dcn21.h | 35 +
.../gpu/drm/amd/display/dc/gpio/hw_factory.c | 8 +
.../drm/amd/display/dc/gpio/hw_translate.c | 8 +
.../gpu/drm/amd/display/dc/inc/core_types.h | 8 +
.../gpu/drm/amd/display/dc/inc/hw/clk_mgr.h | 125 +
.../gpu/drm/amd/display/dc/inc/hw/mem_input.h | 4 +
.../gpu/drm/amd/display/dc/inc/hw_sequencer.h | 1 +
drivers/gpu/drm/amd/display/dc/irq/Makefile | 10 +
.../display/dc/irq/dcn21/irq_service_dcn21.c | 372 +
.../display/dc/irq/dcn21/irq_service_dcn21.h | 34 +
.../gpu/drm/amd/display/include/dal_asic_id.h | 5 +
.../gpu/drm/amd/display/include/dal_types.h | 3 +
.../include/asic_reg/clk/clk_10_0_2_offset.h | 56 +
.../include/asic_reg/clk/clk_10_0_2_sh_mask.h | 73 +
.../include/asic_reg/dcn/dcn_2_1_0_offset.h | 13862 ++++
.../include/asic_reg/dcn/dcn_2_1_0_sh_mask.h | 56638 ++++++++++++++++
.../include/asic_reg/dcn/dpcs_2_1_0_offset.h | 565 +
.../include/asic_reg/dcn/dpcs_2_1_0_sh_mask.h | 3430 +
.../gpu/drm/amd/include/renoir_ip_offset.h | 1364 +
58 files changed, 89383 insertions(+)
create mode 100644 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
create mode 100644 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.h
create mode 100644 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c
create mode 100644 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.h
create mode 100644 drivers/gpu/drm/amd/display/dc/dcn21/Makefile
create mode 100644 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c
create mode 100644 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.h
create mode 100644 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c
create mode 100644 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.h
create mode 100644 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
create mode 100644 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.h
create mode 100644 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
create mode 100644 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.h
create mode 100644 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c
create mode 100644 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.h
create mode 100644 drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_factory_dcn21.c
create mode 100644 drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_factory_dcn21.h
create mode 100644 drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_translate_dcn21.c
create mode 100644 drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_translate_dcn21.h
create mode 100644 drivers/gpu/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.c
create mode 100644 drivers/gpu/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.h
create mode 100644 drivers/gpu/drm/amd/include/asic_reg/clk/clk_10_0_2_offset.h
create mode 100644 drivers/gpu/drm/amd/include/asic_reg/clk/clk_10_0_2_sh_mask.h
create mode 100644 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h
create mode 100644 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_sh_mask.h
create mode 100644 drivers/gpu/drm/amd/include/asic_reg/dcn/dpcs_2_1_0_offset.h
create mode 100644 drivers/gpu/drm/amd/include/asic_reg/dcn/dpcs_2_1_0_sh_mask.h
create mode 100644 drivers/gpu/drm/amd/include/renoir_ip_offset.h
--
2.20.1
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