[PATCH] drm/amd/display: Loading NV10/14 Bounding Box Data Directly From Code
Kazlauskas, Nicholas
nicholas.kazlauskas at amd.com
Tue Dec 3 17:19:03 UTC 2019
On 2019-12-03 12:02 p.m., Zhan Liu wrote:
> [Why]
> NV10/14 has released. Its time to get NV10/14 bounding box
> directly from code.
>
> [How]
> Retrieve NV10/14 bounding box data directly from code.
>
> Signed-off-by: Zhan Liu <zhan.liu at amd.com>
> ---
> .../drm/amd/display/dc/dcn20/dcn20_resource.c | 199 +++++++++++-------
> 1 file changed, 121 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
> index 2ccfd84a7da4..4115b595e36e 100644
> --- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
> +++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
> @@ -83,8 +83,6 @@
>
> #include "amdgpu_socbb.h"
>
> -/* NV12 SOC BB is currently in FW, mark SW bounding box invalid. */
> -#define SOC_BOUNDING_BOX_VALID false
> #define DC_LOGGER_INIT(logger)
>
> struct _vcs_dpi_ip_params_st dcn2_0_ip = {
> @@ -3271,12 +3196,12 @@ static bool init_soc_bounding_box(struct dc *dc,
>
> DC_LOGGER_INIT(dc->ctx->logger);
>
> - if (!bb && !SOC_BOUNDING_BOX_VALID) {
> + if (!bb) {
This will throw an error when we don't have firmware on disk (which now
isn't required for Navi10 or Navi14).
Please replace SOC_BOUNDING_BOX_VALID with a function that has the logic
to check whether the ASIC is Navi12 or not and use it below as well...
> DC_LOG_ERROR("%s: not valid soc bounding box/n", __func__);
> return false;
> }
>
> - if (bb && !SOC_BOUNDING_BOX_VALID) {
> + if (bb && ASICREV_IS_NAVI12_P(dc->ctx->asic_id.hw_internal_rev)) {
...here, eg.
static bool is_soc_bounding_box_valid(uint32_t hw_internal_rev)
{
if (ASICREV_IS_NAVI12_P(hw_internal_rev))
return false;
return true;
}
> int i;
>
> dcn2_0_nv12_soc.sr_exit_time_us =
> @@ -3380,6 +3305,108 @@ static bool init_soc_bounding_box(struct dc *dc,
> }
> }
>
> + if (bb && (ASICREV_IS_NAVI14_M(dc->ctx->asic_id.hw_internal_rev) || ASICREV_IS_NAVI10_P(dc->ctx->asic_id.hw_internal_rev))) {
These constants are already in the table. We shouldn't need to be
filling them in below.
Regards,
Nicholas Kazlauskas
> + dcn2_0_soc.sr_exit_time_us = 8.6;
> + dcn2_0_soc.sr_enter_plus_exit_time_us = 10.9;
> + dcn2_0_soc.urgent_latency_us = 4.0;
> + dcn2_0_soc.urgent_latency_pixel_data_only_us = 4.0;
> + dcn2_0_soc.urgent_latency_pixel_mixed_with_vm_data_us = 4.0;
> + dcn2_0_soc.urgent_latency_vm_data_only_us = 4.0;
> + dcn2_0_soc.urgent_out_of_order_return_per_channel_pixel_only_bytes = 4096;
> + dcn2_0_soc.urgent_out_of_order_return_per_channel_pixel_and_vm_bytes = 4096;
> + dcn2_0_soc.urgent_out_of_order_return_per_channel_vm_only_bytes = 4096;
> + dcn2_0_soc.pct_ideal_dram_sdp_bw_after_urgent_pixel_only = 40.0;
> + dcn2_0_soc.pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm = 40.0;
> + dcn2_0_soc.pct_ideal_dram_sdp_bw_after_urgent_vm_only = 40.0;
> + dcn2_0_soc.max_avg_sdp_bw_use_normal_percent = 40.0;
> + dcn2_0_soc.max_avg_dram_bw_use_normal_percent = 40.0;
> + dcn2_0_soc.writeback_latency_us = 12.0;
> + dcn2_0_soc.ideal_dram_bw_after_urgent_percent = 40.0;
> + dcn2_0_soc.max_request_size_bytes = 256;
> + dcn2_0_soc.dram_channel_width_bytes = 2;
> + dcn2_0_soc.fabric_datapath_to_dcn_data_return_bytes = 64;
> + dcn2_0_soc.dcn_downspread_percent = 0.5;
> + dcn2_0_soc.downspread_percent = 0.38;
> + dcn2_0_soc.dram_page_open_time_ns = 50.0;
> + dcn2_0_soc.dram_rw_turnaround_time_ns = 17.5;
> + dcn2_0_soc.dram_return_buffer_per_channel_bytes = 8192;
> + dcn2_0_soc.round_trip_ping_latency_dcfclk_cycles = 131;
> + dcn2_0_soc.urgent_out_of_order_return_per_channel_bytes = 256;
> + dcn2_0_soc.channel_interleave_bytes = 256;
> + dcn2_0_soc.num_banks = 8;
> + dcn2_0_soc.num_chans = 16;
> + dcn2_0_soc.vmm_page_size_bytes = 4096;
> + dcn2_0_soc.dram_clock_change_latency_us = 404.0;
> + dcn2_0_soc.dummy_pstate_latency_us = 5.0;
> + dcn2_0_soc.writeback_dram_clock_change_latency_us = 23.0;
> + dcn2_0_soc.return_bus_width_bytes = 64;
> + dcn2_0_soc.dispclk_dppclk_vco_speed_mhz = 3850;
> + dcn2_0_soc.xfc_bus_transport_time_us = 20;
> + dcn2_0_soc.xfc_xbuf_latency_tolerance_us = 4;
> + dcn2_0_soc.use_urgent_burst_bw = 0;
> + dcn2_0_soc.num_states = 5;
> +
> + dcn2_0_soc.clock_limits[0].state = 0;
> + dcn2_0_soc.clock_limits[0].dcfclk_mhz = 560.0;
> + dcn2_0_soc.clock_limits[0].fabricclk_mhz = 560.0;
> + dcn2_0_soc.clock_limits[0].dispclk_mhz = 513.0;
> + dcn2_0_soc.clock_limits[0].dppclk_mhz = 513.0;
> + dcn2_0_soc.clock_limits[0].phyclk_mhz = 540.0;
> + dcn2_0_soc.clock_limits[0].socclk_mhz = 560.0;
> + dcn2_0_soc.clock_limits[0].dscclk_mhz = 171.0;
> + dcn2_0_soc.clock_limits[0].dram_speed_mts = 8960.0;
> +
> + dcn2_0_soc.clock_limits[1].state = 1;
> + dcn2_0_soc.clock_limits[1].dcfclk_mhz = 694.0;
> + dcn2_0_soc.clock_limits[1].fabricclk_mhz = 694.0;
> + dcn2_0_soc.clock_limits[1].dispclk_mhz = 642.0;
> + dcn2_0_soc.clock_limits[1].dppclk_mhz = 642.0;
> + dcn2_0_soc.clock_limits[1].phyclk_mhz = 600.0;
> + dcn2_0_soc.clock_limits[1].socclk_mhz = 694.0;
> + dcn2_0_soc.clock_limits[1].dscclk_mhz = 214.0;
> + dcn2_0_soc.clock_limits[1].dram_speed_mts = 11104.0;
> +
> + dcn2_0_soc.clock_limits[2].state = 2;
> + dcn2_0_soc.clock_limits[2].dcfclk_mhz = 875.0;
> + dcn2_0_soc.clock_limits[2].fabricclk_mhz = 875.0;
> + dcn2_0_soc.clock_limits[2].dispclk_mhz = 734.0;
> + dcn2_0_soc.clock_limits[2].dppclk_mhz = 734.0;
> + dcn2_0_soc.clock_limits[2].phyclk_mhz = 810.0;
> + dcn2_0_soc.clock_limits[2].socclk_mhz = 875.0;
> + dcn2_0_soc.clock_limits[2].dscclk_mhz = 245.0;
> + dcn2_0_soc.clock_limits[2].dram_speed_mts = 14000.0;
> +
> + dcn2_0_soc.clock_limits[3].state = 3;
> + dcn2_0_soc.clock_limits[3].dcfclk_mhz = 1000.0;
> + dcn2_0_soc.clock_limits[3].fabricclk_mhz = 1000.0;
> + dcn2_0_soc.clock_limits[3].dispclk_mhz = 1100.0;
> + dcn2_0_soc.clock_limits[3].dppclk_mhz = 1100.0;
> + dcn2_0_soc.clock_limits[3].phyclk_mhz = 810.0;
> + dcn2_0_soc.clock_limits[3].socclk_mhz = 1000.0;
> + dcn2_0_soc.clock_limits[3].dscclk_mhz = 367.0;
> + dcn2_0_soc.clock_limits[3].dram_speed_mts = 16000.0;
> +
> + dcn2_0_soc.clock_limits[4].state = 4;
> + dcn2_0_soc.clock_limits[4].dcfclk_mhz = 1200.0;
> + dcn2_0_soc.clock_limits[4].fabricclk_mhz = 1200.0;
> + dcn2_0_soc.clock_limits[4].dispclk_mhz = 1284.0;
> + dcn2_0_soc.clock_limits[4].dppclk_mhz = 1284.0;
> + dcn2_0_soc.clock_limits[4].phyclk_mhz = 810.0;
> + dcn2_0_soc.clock_limits[4].socclk_mhz = 1200.0;
> + dcn2_0_soc.clock_limits[4].dscclk_mhz = 428.0;
> + dcn2_0_soc.clock_limits[4].dram_speed_mts = 16000.0;
> +
> + dcn2_0_soc.clock_limits[5].state = 5;
> + dcn2_0_soc.clock_limits[5].dcfclk_mhz = 1200.0;
> + dcn2_0_soc.clock_limits[5].fabricclk_mhz = 1200.0;
> + dcn2_0_soc.clock_limits[5].dispclk_mhz = 1284.0;
> + dcn2_0_soc.clock_limits[5].dppclk_mhz = 1284.0;
> + dcn2_0_soc.clock_limits[5].phyclk_mhz = 810.0;
> + dcn2_0_soc.clock_limits[5].socclk_mhz = 1200.0;
> + dcn2_0_soc.clock_limits[5].dscclk_mhz = 428.0;
> + dcn2_0_soc.clock_limits[5].dram_speed_mts = 16000.0;
> + }
> +
> if (pool->base.pp_smu) {
> struct pp_smu_nv_clock_table max_clocks = {0};
> unsigned int uclk_states[8] = {0};
>
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