[PATCH 27/39] drm/amd/display: Get cache window sizes from DMCUB firmware
Rodrigo Siqueira
Rodrigo.Siqueira at amd.com
Wed Dec 11 15:32:41 UTC 2019
From: Nicholas Kazlauskas <nicholas.kazlauskas at amd.com>
[Why]
Firmware state and tracebuffer shouldn't be considered stable API
between firmware versions.
Driver shouldn't be querying anything from firmware state or tracebuffer
outside of debugging.
Commands are the stable API for this once we have the outbox.
[How]
Add metadata struct to the end of the data firmware that describes
fw_state_size and some reserved area for future use.
Drop the tracebuffer and firmware state headers since they can differ
per version.
Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas at amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng at amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira at amd.com>
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 4 ++
.../inc/{dmub_fw_state.h => dmub_fw_meta.h} | 64 ++++++++-----------
.../gpu/drm/amd/display/dmub/inc/dmub_srv.h | 3 +-
.../gpu/drm/amd/display/dmub/src/dmub_srv.c | 51 +++++++++++++--
4 files changed, 78 insertions(+), 44 deletions(-)
rename drivers/gpu/drm/amd/display/dmub/inc/{dmub_fw_state.h => dmub_fw_meta.h} (57%)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 8cdfb3ccb710..745d8719ccc1 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -1234,6 +1234,10 @@ static int dm_dmub_sw_init(struct amdgpu_device *adev)
PSP_HEADER_BYTES - PSP_FOOTER_BYTES;
region_params.bss_data_size = le32_to_cpu(hdr->bss_data_bytes);
region_params.vbios_size = adev->bios_size;
+ region_params.fw_bss_data =
+ adev->dm.dmub_fw->data +
+ le32_to_cpu(hdr->header.ucode_array_offset_bytes) +
+ le32_to_cpu(hdr->inst_const_bytes);
status = dmub_srv_calc_region_info(dmub_srv, ®ion_params,
®ion_info);
diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_fw_state.h b/drivers/gpu/drm/amd/display/dmub/inc/dmub_fw_meta.h
similarity index 57%
rename from drivers/gpu/drm/amd/display/dmub/inc/dmub_fw_state.h
rename to drivers/gpu/drm/amd/display/dmub/inc/dmub_fw_meta.h
index c87b1ba7590e..242ec257998c 100644
--- a/drivers/gpu/drm/amd/display/dmub/inc/dmub_fw_state.h
+++ b/drivers/gpu/drm/amd/display/dmub/inc/dmub_fw_meta.h
@@ -22,52 +22,42 @@
* Authors: AMD
*
*/
-
-#ifndef _DMUB_FW_STATE_H_
-#define _DMUB_FW_STATE_H_
+#ifndef _DMUB_META_H_
+#define _DMUB_META_H_
#include "dmub_types.h"
#pragma pack(push, 1)
-struct dmub_fw_state {
- /**
- * @phy_initialized_during_fw_boot:
- *
- * Detects if VBIOS/VBL has ran before firmware boot.
- * A value of 1 will usually mean S0i3 boot.
- */
- uint8_t phy_initialized_during_fw_boot;
-
- /**
- * @intialized_phy:
- *
- * Bit vector of initialized PHY.
- */
- uint8_t initialized_phy;
+/* Magic value for identifying dmub_fw_meta_info */
+#define DMUB_FW_META_MAGIC 0x444D5542
- /**
- * @enabled_phy:
- *
- * Bit vector of enabled PHY for DP alt mode switch tracking.
- */
- uint8_t enabled_phy;
+/* Offset from the end of the file to the dmub_fw_meta_info */
+#define DMUB_FW_META_OFFSET 0x24
- /**
- * @dmcu_fw_loaded:
- *
- * DMCU auto load state.
- */
- uint8_t dmcu_fw_loaded;
+/**
+ * struct dmub_fw_meta_info - metadata associated with fw binary
+ *
+ * NOTE: This should be considered a stable API. Fields should
+ * not be repurposed or reordered. New fields should be
+ * added instead to extend the structure.
+ *
+ * @magic_value: magic value identifying DMUB firmware meta info
+ * @fw_region_size: size of the firmware state region
+ * @trace_buffer_size: size of the tracebuffer region
+ */
+struct dmub_fw_meta_info {
+ uint32_t magic_value;
+ uint32_t fw_region_size;
+ uint32_t trace_buffer_size;
+};
- /**
- * @psr_state:
- *
- * PSR state tracking.
- */
- uint8_t psr_state;
+/* Ensure that the structure remains 64 bytes. */
+union dmub_fw_meta {
+ struct dmub_fw_meta_info info;
+ uint8_t reserved[64];
};
#pragma pack(pop)
-#endif /* _DMUB_FW_STATE_H_ */
+#endif /* _DMUB_META_H_ */
diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_srv.h b/drivers/gpu/drm/amd/display/dmub/inc/dmub_srv.h
index 689806b6ee31..f34a50dd36ea 100644
--- a/drivers/gpu/drm/amd/display/dmub/inc/dmub_srv.h
+++ b/drivers/gpu/drm/amd/display/dmub/inc/dmub_srv.h
@@ -67,7 +67,6 @@
#include "dmub_types.h"
#include "dmub_cmd.h"
#include "dmub_rb.h"
-#include "dmub_fw_state.h"
#if defined(__cplusplus)
extern "C" {
@@ -145,11 +144,13 @@ struct dmub_fb {
* @inst_const_size: size of the fw inst const section
* @bss_data_size: size of the fw bss data section
* @vbios_size: size of the vbios data
+ * @fw_bss_data: raw firmware bss data section
*/
struct dmub_srv_region_params {
uint32_t inst_const_size;
uint32_t bss_data_size;
uint32_t vbios_size;
+ const uint8_t *fw_bss_data;
};
/**
diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c b/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c
index 16837003721e..9a959f871f11 100644
--- a/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c
+++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c
@@ -26,7 +26,7 @@
#include "../inc/dmub_srv.h"
#include "dmub_dcn20.h"
#include "dmub_dcn21.h"
-#include "dmub_trace_buffer.h"
+#include "dmub_fw_meta.h"
#include "os_types.h"
/*
* Note: the DMUB service is standalone. No additional headers should be
@@ -46,6 +46,11 @@
/* Mailbox size */
#define DMUB_MAILBOX_SIZE (DMUB_RB_SIZE)
+/* Default state size if meta is absent. */
+#define DMUB_FW_STATE_SIZE (1024)
+
+/* Default tracebuffer size if meta is absent. */
+#define DMUB_TRACE_BUFFER_SIZE (1024)
/* Number of windows in use. */
#define DMUB_NUM_WINDOWS (DMUB_WINDOW_6_FW_STATE + 1)
@@ -62,6 +67,27 @@ static inline uint32_t dmub_align(uint32_t val, uint32_t factor)
return (val + factor - 1) / factor * factor;
}
+static const struct dmub_fw_meta_info *
+dmub_get_fw_meta_info(const uint8_t *fw_bss_data, uint32_t fw_bss_data_size)
+{
+ const union dmub_fw_meta *meta;
+
+ if (fw_bss_data == NULL)
+ return NULL;
+
+ if (fw_bss_data_size < sizeof(union dmub_fw_meta) + DMUB_FW_META_OFFSET)
+ return NULL;
+
+ meta = (const union dmub_fw_meta *)(fw_bss_data + fw_bss_data_size -
+ DMUB_FW_META_OFFSET -
+ sizeof(union dmub_fw_meta));
+
+ if (meta->info.magic_value != DMUB_FW_META_MAGIC)
+ return NULL;
+
+ return &meta->info;
+}
+
static bool dmub_srv_hw_setup(struct dmub_srv *dmub, enum dmub_asic asic)
{
struct dmub_srv_hw_funcs *funcs = &dmub->hw_funcs;
@@ -162,6 +188,9 @@ dmub_srv_calc_region_info(struct dmub_srv *dmub,
struct dmub_region *mail = &out->regions[DMUB_WINDOW_4_MAILBOX];
struct dmub_region *trace_buff = &out->regions[DMUB_WINDOW_5_TRACEBUFF];
struct dmub_region *fw_state = &out->regions[DMUB_WINDOW_6_FW_STATE];
+ const struct dmub_fw_meta_info *fw_info;
+ uint32_t fw_state_size = DMUB_FW_STATE_SIZE;
+ uint32_t trace_buffer_size = DMUB_TRACE_BUFFER_SIZE;
if (!dmub->sw_init)
return DMUB_STATUS_INVALID;
@@ -176,6 +205,11 @@ dmub_srv_calc_region_info(struct dmub_srv *dmub,
data->base = dmub_align(inst->top, 256);
data->top = data->base + params->bss_data_size;
+ /*
+ * All cache windows below should be aligned to the size
+ * of the DMCUB cache line, 64 bytes.
+ */
+
stack->base = dmub_align(data->top, 256);
stack->top = stack->base + DMUB_STACK_SIZE + DMUB_CONTEXT_SIZE;
@@ -185,14 +219,19 @@ dmub_srv_calc_region_info(struct dmub_srv *dmub,
mail->base = dmub_align(bios->top, 256);
mail->top = mail->base + DMUB_MAILBOX_SIZE;
+ fw_info = dmub_get_fw_meta_info(params->fw_bss_data,
+ params->bss_data_size);
+
+ if (fw_info) {
+ fw_state_size = fw_info->fw_region_size;
+ trace_buffer_size = fw_info->trace_buffer_size;
+ }
+
trace_buff->base = dmub_align(mail->top, 256);
- trace_buff->top = trace_buff->base + TRACE_BUF_SIZE;
+ trace_buff->top = trace_buff->base + dmub_align(trace_buffer_size, 64);
fw_state->base = dmub_align(trace_buff->top, 256);
-
- /* Align firmware state to size of cache line. */
- fw_state->top =
- fw_state->base + dmub_align(sizeof(struct dmub_fw_state), 64);
+ fw_state->top = fw_state->base + dmub_align(fw_state_size, 64);
out->fb_size = dmub_align(fw_state->top, 4096);
--
2.24.0
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