[PATCH 1/3] amdgpu: Prepare DCN floating point macros for generic
Alex Deucher
alexdeucher at gmail.com
Thu Dec 12 22:41:25 UTC 2019
On Sat, Dec 7, 2019 at 5:47 PM Timothy Pearson
<tpearson at raptorengineering.com> wrote:
>
> arch support
>
> Introduce DC_FP_START()/DC_FP_END() macros to help enable floating
> point kernel mode support across various architectures.
>
> Signed-off-by: Timothy Pearson <tpearson at raptorengineering.com>
Applied with a bit of tweaking. Thanks!
Alex
> ---
> .../gpu/drm/amd/display/dc/calcs/dcn_calcs.c | 24 +++++++++----------
> .../drm/amd/display/dc/dcn20/dcn20_resource.c | 4 ++--
> .../drm/amd/display/dc/dcn21/dcn21_resource.c | 4 ++--
> drivers/gpu/drm/amd/display/dc/os_types.h | 3 +++
> 4 files changed, 19 insertions(+), 16 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
> index 9b2cb57bf2ba..cd5471263248 100644
> --- a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
> +++ b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
> @@ -626,7 +626,7 @@ static bool dcn_bw_apply_registry_override(struct dc *dc)
> {
> bool updated = false;
>
> - kernel_fpu_begin();
> + DC_FP_START();
> if ((int)(dc->dcn_soc->sr_exit_time * 1000) != dc->debug.sr_exit_time_ns
> && dc->debug.sr_exit_time_ns) {
> updated = true;
> @@ -662,7 +662,7 @@ static bool dcn_bw_apply_registry_override(struct dc *dc)
> dc->dcn_soc->dram_clock_change_latency =
> dc->debug.dram_clock_change_latency_ns / 1000.0;
> }
> - kernel_fpu_end();
> + DC_FP_END();
>
> return updated;
> }
> @@ -742,7 +742,7 @@ bool dcn_validate_bandwidth(
> dcn_bw_sync_calcs_and_dml(dc);
>
> memset(v, 0, sizeof(*v));
> - kernel_fpu_begin();
> + DC_FP_START();
>
> v->sr_exit_time = dc->dcn_soc->sr_exit_time;
> v->sr_enter_plus_exit_time = dc->dcn_soc->sr_enter_plus_exit_time;
> @@ -1275,7 +1275,7 @@ bool dcn_validate_bandwidth(
> bw_limit = dc->dcn_soc->percent_disp_bw_limit * v->fabric_and_dram_bandwidth_vmax0p9;
> bw_limit_pass = (v->total_data_read_bandwidth / 1000.0) < bw_limit;
>
> - kernel_fpu_end();
> + DC_FP_END();
>
> PERFORMANCE_TRACE_END();
> BW_VAL_TRACE_FINISH();
> @@ -1443,7 +1443,7 @@ void dcn_bw_update_from_pplib(struct dc *dc)
> res = dm_pp_get_clock_levels_by_type_with_voltage(
> ctx, DM_PP_CLOCK_TYPE_FCLK, &fclks);
>
> - kernel_fpu_begin();
> + DC_FP_START();
>
> if (res)
> res = verify_clock_values(&fclks);
> @@ -1463,12 +1463,12 @@ void dcn_bw_update_from_pplib(struct dc *dc)
> } else
> BREAK_TO_DEBUGGER();
>
> - kernel_fpu_end();
> + DC_FP_END();
>
> res = dm_pp_get_clock_levels_by_type_with_voltage(
> ctx, DM_PP_CLOCK_TYPE_DCFCLK, &dcfclks);
>
> - kernel_fpu_begin();
> + DC_FP_START();
>
> if (res)
> res = verify_clock_values(&dcfclks);
> @@ -1481,7 +1481,7 @@ void dcn_bw_update_from_pplib(struct dc *dc)
> } else
> BREAK_TO_DEBUGGER();
>
> - kernel_fpu_end();
> + DC_FP_END();
> }
>
> void dcn_bw_notify_pplib_of_wm_ranges(struct dc *dc)
> @@ -1496,11 +1496,11 @@ void dcn_bw_notify_pplib_of_wm_ranges(struct dc *dc)
> if (!pp || !pp->set_wm_ranges)
> return;
>
> - kernel_fpu_begin();
> + DC_FP_START();
> min_fclk_khz = dc->dcn_soc->fabric_and_dram_bandwidth_vmin0p65 * 1000000 / 32;
> min_dcfclk_khz = dc->dcn_soc->dcfclkv_min0p65 * 1000;
> socclk_khz = dc->dcn_soc->socclk * 1000;
> - kernel_fpu_end();
> + DC_FP_END();
>
> /* Now notify PPLib/SMU about which Watermarks sets they should select
> * depending on DPM state they are in. And update BW MGR GFX Engine and
> @@ -1551,7 +1551,7 @@ void dcn_bw_notify_pplib_of_wm_ranges(struct dc *dc)
>
> void dcn_bw_sync_calcs_and_dml(struct dc *dc)
> {
> - kernel_fpu_begin();
> + DC_FP_START();
> DC_LOG_BANDWIDTH_CALCS("sr_exit_time: %f ns\n"
> "sr_enter_plus_exit_time: %f ns\n"
> "urgent_latency: %f ns\n"
> @@ -1740,5 +1740,5 @@ void dcn_bw_sync_calcs_and_dml(struct dc *dc)
> dc->dml.ip.bug_forcing_LC_req_same_size_fixed =
> dc->dcn_ip->bug_forcing_luma_and_chroma_request_to_same_size_fixed == dcn_bw_yes;
> dc->dml.ip.dcfclk_cstate_latency = dc->dcn_ip->dcfclk_cstate_latency;
> - kernel_fpu_end();
> + DC_FP_END();
> }
> diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
> index 09793336d84f..74ad6f09c1d4 100644
> --- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
> +++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
> @@ -3243,7 +3243,7 @@ void dcn20_update_bounding_box(struct dc *dc, struct _vcs_dpi_soc_bounding_box_s
>
> void dcn20_patch_bounding_box(struct dc *dc, struct _vcs_dpi_soc_bounding_box_st *bb)
> {
> - kernel_fpu_begin();
> + DC_FP_START();
> if ((int)(bb->sr_exit_time_us * 1000) != dc->bb_overrides.sr_exit_time_ns
> && dc->bb_overrides.sr_exit_time_ns) {
> bb->sr_exit_time_us = dc->bb_overrides.sr_exit_time_ns / 1000.0;
> @@ -3267,7 +3267,7 @@ void dcn20_patch_bounding_box(struct dc *dc, struct _vcs_dpi_soc_bounding_box_st
> bb->dram_clock_change_latency_us =
> dc->bb_overrides.dram_clock_change_latency_ns / 1000.0;
> }
> - kernel_fpu_end();
> + DC_FP_END();
> }
>
> static struct _vcs_dpi_soc_bounding_box_st *get_asic_rev_soc_bb(
> diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
> index 459bd9a5caed..ce4d38e91054 100644
> --- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
> +++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
> @@ -1017,7 +1017,7 @@ static void calculate_wm_set_for_vlevel(
>
> static void patch_bounding_box(struct dc *dc, struct _vcs_dpi_soc_bounding_box_st *bb)
> {
> - kernel_fpu_begin();
> + DC_FP_START();
> if (dc->bb_overrides.sr_exit_time_ns) {
> bb->sr_exit_time_us = dc->bb_overrides.sr_exit_time_ns / 1000.0;
> }
> @@ -1035,7 +1035,7 @@ static void patch_bounding_box(struct dc *dc, struct _vcs_dpi_soc_bounding_box_s
> bb->dram_clock_change_latency_us =
> dc->bb_overrides.dram_clock_change_latency_ns / 1000.0;
> }
> - kernel_fpu_end();
> + DC_FP_END();
> }
>
> void dcn21_calculate_wm(
> diff --git a/drivers/gpu/drm/amd/display/dc/os_types.h b/drivers/gpu/drm/amd/display/dc/os_types.h
> index 30ec80ac6fc8..938735bf624d 100644
> --- a/drivers/gpu/drm/amd/display/dc/os_types.h
> +++ b/drivers/gpu/drm/amd/display/dc/os_types.h
> @@ -1,5 +1,6 @@
> /*
> * Copyright 2012-16 Advanced Micro Devices, Inc.
> + * Copyright 2019 Raptor Engineering, LLC
> *
> * Permission is hereby granted, free of charge, to any person obtaining a
> * copy of this software and associated documentation files (the "Software"),
> @@ -50,6 +51,8 @@
>
> #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
> #include <asm/fpu/api.h>
> +#define DC_FP_START() kernel_fpu_begin()
> +#define DC_FP_END() kernel_fpu_end()
> #endif
>
> /*
> --
> 2.20.1
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