[PATCH 3/3] drm/amd/display: add missing dcn link encoder regs
Harry Wentland
hwentlan at amd.com
Fri Dec 13 20:57:12 UTC 2019
Series is
Reviewed-by: Harry Wentland <harry.wentland at amd.com>
Harry
On 2019-12-11 10:45 a.m., Roman.Li at amd.com wrote:
> From: Roman Li <Roman.Li at amd.com>
>
> [Why]
> The earlier change: "check phy dpalt lane count config"
> uses link encoder registers not defined properly.
> That caused regression with mst-enabled display not
> lighting up.
>
> [How]
> Add missing reg definitions.
>
> Signed-off-by: Roman Li <Roman.Li at amd.com>
> ---
> .../drm/amd/display/dc/dcn10/dcn10_link_encoder.h | 20 +++
> .../drm/amd/display/dc/dcn20/dcn20_link_encoder.h | 180 ++++++++++++++++++++-
> .../gpu/drm/amd/display/dc/dcn20/dcn20_resource.c | 9 +-
> .../drm/amd/display/dc/dcn21/dcn21_link_encoder.h | 39 +++++
> .../gpu/drm/amd/display/dc/dcn21/dcn21_resource.c | 11 +-
> 5 files changed, 253 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h
> index 7493a63..eb13589 100644
> --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h
> +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h
> @@ -124,6 +124,26 @@ struct dcn10_link_enc_registers {
> uint32_t RDPCSTX_PHY_CNTL13;
> uint32_t RDPCSTX_PHY_CNTL14;
> uint32_t RDPCSTX_PHY_CNTL15;
> + uint32_t RDPCSTX_CNTL;
> + uint32_t RDPCSTX_CLOCK_CNTL;
> + uint32_t RDPCSTX_PHY_CNTL0;
> + uint32_t RDPCSTX_PHY_CNTL2;
> + uint32_t RDPCSTX_PLL_UPDATE_DATA;
> + uint32_t RDPCS_TX_CR_ADDR;
> + uint32_t RDPCS_TX_CR_DATA;
> + uint32_t DPCSTX_TX_CLOCK_CNTL;
> + uint32_t DPCSTX_TX_CNTL;
> + uint32_t RDPCSTX_INTERRUPT_CONTROL;
> + uint32_t RDPCSTX_PHY_FUSE0;
> + uint32_t RDPCSTX_PHY_FUSE1;
> + uint32_t RDPCSTX_PHY_FUSE2;
> + uint32_t RDPCSTX_PHY_FUSE3;
> + uint32_t RDPCSTX_PHY_RX_LD_VAL;
> + uint32_t DPCSTX_DEBUG_CONFIG;
> + uint32_t RDPCSTX_DEBUG_CONFIG;
> + uint32_t RDPCSTX0_RDPCSTX_SCRATCH;
> + uint32_t RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG;
> + uint32_t DCIO_SOFT_RESET;
> /* indirect registers */
> uint32_t RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2;
> uint32_t RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3;
> diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.h b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.h
> index 62dfd34..8cab810 100644
> --- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.h
> +++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.h
> @@ -33,7 +33,142 @@
> SRI(AUX_DPHY_TX_CONTROL, DP_AUX, id)
>
> #define UNIPHY_MASK_SH_LIST(mask_sh)\
> - LE_SF(UNIPHYA_CHANNEL_XBAR_CNTL, UNIPHY_LINK_ENABLE, mask_sh)
> + LE_SF(SYMCLKA_CLOCK_ENABLE, SYMCLKA_CLOCK_ENABLE, mask_sh),\
> + LE_SF(UNIPHYA_CHANNEL_XBAR_CNTL, UNIPHY_LINK_ENABLE, mask_sh),\
> + LE_SF(UNIPHYA_CHANNEL_XBAR_CNTL, UNIPHY_CHANNEL0_XBAR_SOURCE, mask_sh),\
> + LE_SF(UNIPHYA_CHANNEL_XBAR_CNTL, UNIPHY_CHANNEL1_XBAR_SOURCE, mask_sh),\
> + LE_SF(UNIPHYA_CHANNEL_XBAR_CNTL, UNIPHY_CHANNEL2_XBAR_SOURCE, mask_sh),\
> + LE_SF(UNIPHYA_CHANNEL_XBAR_CNTL, UNIPHY_CHANNEL3_XBAR_SOURCE, mask_sh)
> +
> +#define DPCS_MASK_SH_LIST(mask_sh)\
> + LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX0_CLK_RDY, mask_sh),\
> + LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX0_DATA_EN, mask_sh),\
> + LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX1_CLK_RDY, mask_sh),\
> + LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX1_DATA_EN, mask_sh),\
> + LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX2_CLK_RDY, mask_sh),\
> + LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX2_DATA_EN, mask_sh),\
> + LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX3_CLK_RDY, mask_sh),\
> + LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX3_DATA_EN, mask_sh),\
> + LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL4, RDPCS_PHY_DP_TX0_TERM_CTRL, mask_sh),\
> + LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL4, RDPCS_PHY_DP_TX1_TERM_CTRL, mask_sh),\
> + LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL4, RDPCS_PHY_DP_TX2_TERM_CTRL, mask_sh),\
> + LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL4, RDPCS_PHY_DP_TX3_TERM_CTRL, mask_sh),\
> + LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL11, RDPCS_PHY_DP_MPLLB_MULTIPLIER, mask_sh),\
> + LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL5, RDPCS_PHY_DP_TX0_WIDTH, mask_sh),\
> + LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL5, RDPCS_PHY_DP_TX0_RATE, mask_sh),\
> + LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL5, RDPCS_PHY_DP_TX1_WIDTH, mask_sh),\
> + LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL5, RDPCS_PHY_DP_TX1_RATE, mask_sh),\
> + LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL6, RDPCS_PHY_DP_TX2_PSTATE, mask_sh),\
> + LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL6, RDPCS_PHY_DP_TX3_PSTATE, mask_sh),\
> + LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL6, RDPCS_PHY_DP_TX2_MPLL_EN, mask_sh),\
> + LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL6, RDPCS_PHY_DP_TX3_MPLL_EN, mask_sh),\
> + LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL7, RDPCS_PHY_DP_MPLLB_FRACN_QUOT, mask_sh),\
> + LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL7, RDPCS_PHY_DP_MPLLB_FRACN_DEN, mask_sh),\
> + LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL8, RDPCS_PHY_DP_MPLLB_SSC_PEAK, mask_sh),\
> + LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL9, RDPCS_PHY_DP_MPLLB_SSC_UP_SPREAD, mask_sh),\
> + LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL9, RDPCS_PHY_DP_MPLLB_SSC_STEPSIZE, mask_sh),\
> + LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL10, RDPCS_PHY_DP_MPLLB_FRACN_REM, mask_sh),\
> + LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL11, RDPCS_PHY_DP_REF_CLK_MPLLB_DIV, mask_sh),\
> + LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL11, RDPCS_PHY_HDMI_MPLLB_HDMI_DIV, mask_sh),\
> + LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL12, RDPCS_PHY_DP_MPLLB_SSC_EN, mask_sh),\
> + LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL12, RDPCS_PHY_DP_MPLLB_DIV5_CLK_EN, mask_sh),\
> + LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL12, RDPCS_PHY_DP_MPLLB_TX_CLK_DIV, mask_sh),\
> + LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL12, RDPCS_PHY_DP_MPLLB_WORD_DIV2_EN, mask_sh),\
> + LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL12, RDPCS_PHY_DP_MPLLB_STATE, mask_sh),\
> + LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL13, RDPCS_PHY_DP_MPLLB_DIV_CLK_EN, mask_sh),\
> + LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL13, RDPCS_PHY_DP_MPLLB_DIV_MULTIPLIER, mask_sh),\
> + LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL14, RDPCS_PHY_DP_MPLLB_FRACN_EN, mask_sh),\
> + LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL14, RDPCS_PHY_DP_MPLLB_PMIX_EN, mask_sh),\
> + LE_SF(RDPCSTX0_RDPCSTX_CNTL, RDPCS_TX_FIFO_LANE0_EN, mask_sh),\
> + LE_SF(RDPCSTX0_RDPCSTX_CNTL, RDPCS_TX_FIFO_LANE1_EN, mask_sh),\
> + LE_SF(RDPCSTX0_RDPCSTX_CNTL, RDPCS_TX_FIFO_LANE2_EN, mask_sh),\
> + LE_SF(RDPCSTX0_RDPCSTX_CNTL, RDPCS_TX_FIFO_LANE3_EN, mask_sh),\
> + LE_SF(RDPCSTX0_RDPCSTX_CNTL, RDPCS_TX_FIFO_EN, mask_sh),\
> + LE_SF(RDPCSTX0_RDPCSTX_CNTL, RDPCS_TX_FIFO_RD_START_DELAY, mask_sh),\
> + LE_SF(RDPCSTX0_RDPCSTX_CLOCK_CNTL, RDPCS_EXT_REFCLK_EN, mask_sh),\
> + LE_SF(RDPCSTX0_RDPCSTX_CLOCK_CNTL, RDPCS_SRAMCLK_BYPASS, mask_sh),\
> + LE_SF(RDPCSTX0_RDPCSTX_CLOCK_CNTL, RDPCS_SRAMCLK_EN, mask_sh),\
> + LE_SF(RDPCSTX0_RDPCSTX_CLOCK_CNTL, RDPCS_SRAMCLK_CLOCK_ON, mask_sh),\
> + LE_SF(RDPCSTX0_RDPCSTX_CLOCK_CNTL, RDPCS_SYMCLK_DIV2_CLOCK_ON, mask_sh),\
> + LE_SF(RDPCSTX0_RDPCSTX_CLOCK_CNTL, RDPCS_SYMCLK_DIV2_GATE_DIS, mask_sh),\
> + LE_SF(RDPCSTX0_RDPCSTX_CLOCK_CNTL, RDPCS_SYMCLK_DIV2_EN, mask_sh),\
> + LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX0_DISABLE, mask_sh),\
> + LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX1_DISABLE, mask_sh),\
> + LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX2_DISABLE, mask_sh),\
> + LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX3_DISABLE, mask_sh),\
> + LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX0_REQ, mask_sh),\
> + LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX1_REQ, mask_sh),\
> + LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX2_REQ, mask_sh),\
> + LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX3_REQ, mask_sh),\
> + LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX0_ACK, mask_sh),\
> + LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX1_ACK, mask_sh),\
> + LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX2_ACK, mask_sh),\
> + LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX3_ACK, mask_sh),\
> + LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX0_RESET, mask_sh),\
> + LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX1_RESET, mask_sh),\
> + LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX2_RESET, mask_sh),\
> + LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX3_RESET, mask_sh),\
> + LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL0, RDPCS_PHY_RESET, mask_sh),\
> + LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL0, RDPCS_PHY_CR_MUX_SEL, mask_sh),\
> + LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL0, RDPCS_PHY_REF_RANGE, mask_sh),\
> + LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL0, RDPCS_SRAM_BYPASS, mask_sh),\
> + LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL0, RDPCS_SRAM_EXT_LD_DONE, mask_sh),\
> + LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL0, RDPCS_PHY_HDMIMODE_ENABLE, mask_sh),\
> + LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL0, RDPCS_SRAM_INIT_DONE, mask_sh),\
> + LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL2, RDPCS_PHY_DP4_POR, mask_sh),\
> + LE_SF(RDPCSTX0_RDPCSTX_PLL_UPDATE_DATA, RDPCS_PLL_UPDATE_DATA, mask_sh),\
> + LE_SF(RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL, RDPCS_REG_FIFO_ERROR_MASK, mask_sh),\
> + LE_SF(RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL, RDPCS_TX_FIFO_ERROR_MASK, mask_sh),\
> + LE_SF(RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL, RDPCS_DPALT_DISABLE_TOGGLE_MASK, mask_sh),\
> + LE_SF(RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL, RDPCS_DPALT_4LANE_TOGGLE_MASK, mask_sh),\
> + LE_SF(RDPCSTX0_RDPCS_TX_CR_ADDR, RDPCS_TX_CR_ADDR, mask_sh),\
> + LE_SF(RDPCSTX0_RDPCS_TX_CR_DATA, RDPCS_TX_CR_DATA, mask_sh),\
> + LE_SF(RDPCSTX0_RDPCSTX_PHY_FUSE0, RDPCS_PHY_DP_MPLLB_V2I, mask_sh),\
> + LE_SF(RDPCSTX0_RDPCSTX_PHY_FUSE0, RDPCS_PHY_DP_TX0_EQ_MAIN, mask_sh),\
> + LE_SF(RDPCSTX0_RDPCSTX_PHY_FUSE0, RDPCS_PHY_DP_TX0_EQ_PRE, mask_sh),\
> + LE_SF(RDPCSTX0_RDPCSTX_PHY_FUSE0, RDPCS_PHY_DP_TX0_EQ_POST, mask_sh),\
> + LE_SF(RDPCSTX0_RDPCSTX_PHY_FUSE0, RDPCS_PHY_DP_MPLLB_FREQ_VCO, mask_sh),\
> + LE_SF(RDPCSTX0_RDPCSTX_PHY_FUSE1, RDPCS_PHY_DP_MPLLB_CP_INT, mask_sh),\
> + LE_SF(RDPCSTX0_RDPCSTX_PHY_FUSE1, RDPCS_PHY_DP_MPLLB_CP_PROP, mask_sh),\
> + LE_SF(RDPCSTX0_RDPCSTX_PHY_FUSE1, RDPCS_PHY_DP_TX1_EQ_MAIN, mask_sh),\
> + LE_SF(RDPCSTX0_RDPCSTX_PHY_FUSE1, RDPCS_PHY_DP_TX1_EQ_PRE, mask_sh),\
> + LE_SF(RDPCSTX0_RDPCSTX_PHY_FUSE1, RDPCS_PHY_DP_TX1_EQ_POST, mask_sh),\
> + LE_SF(RDPCSTX0_RDPCSTX_PHY_FUSE2, RDPCS_PHY_DP_TX2_EQ_MAIN, mask_sh),\
> + LE_SF(RDPCSTX0_RDPCSTX_PHY_FUSE2, RDPCS_PHY_DP_TX2_EQ_PRE, mask_sh),\
> + LE_SF(RDPCSTX0_RDPCSTX_PHY_FUSE2, RDPCS_PHY_DP_TX2_EQ_POST, mask_sh),\
> + LE_SF(RDPCSTX0_RDPCSTX_PHY_FUSE3, RDPCS_PHY_DP_TX3_EQ_MAIN, mask_sh),\
> + LE_SF(RDPCSTX0_RDPCSTX_PHY_FUSE3, RDPCS_PHY_DCO_FINETUNE, mask_sh),\
> + LE_SF(RDPCSTX0_RDPCSTX_PHY_FUSE3, RDPCS_PHY_DCO_RANGE, mask_sh),\
> + LE_SF(RDPCSTX0_RDPCSTX_PHY_FUSE3, RDPCS_PHY_DP_TX3_EQ_PRE, mask_sh),\
> + LE_SF(RDPCSTX0_RDPCSTX_PHY_FUSE3, RDPCS_PHY_DP_TX3_EQ_POST, mask_sh),\
> + LE_SF(DPCSTX0_DPCSTX_TX_CLOCK_CNTL, DPCS_SYMCLK_CLOCK_ON, mask_sh),\
> + LE_SF(DPCSTX0_DPCSTX_TX_CLOCK_CNTL, DPCS_SYMCLK_GATE_DIS, mask_sh),\
> + LE_SF(DPCSTX0_DPCSTX_TX_CLOCK_CNTL, DPCS_SYMCLK_EN, mask_sh),\
> + LE_SF(DPCSTX0_DPCSTX_TX_CNTL, DPCS_TX_DATA_SWAP, mask_sh),\
> + LE_SF(DPCSTX0_DPCSTX_TX_CNTL, DPCS_TX_DATA_ORDER_INVERT, mask_sh),\
> + LE_SF(DPCSTX0_DPCSTX_TX_CNTL, DPCS_TX_FIFO_EN, mask_sh),\
> + LE_SF(DPCSTX0_DPCSTX_TX_CNTL, DPCS_TX_FIFO_RD_START_DELAY, mask_sh),\
> + LE_SF(DPCSTX0_DPCSTX_DEBUG_CONFIG, DPCS_DBG_CBUS_DIS, mask_sh)
> +
> +#define DPCS_DCN2_MASK_SH_LIST(mask_sh)\
> + DPCS_MASK_SH_LIST(mask_sh),\
> + LE_SF(RDPCSTX0_RDPCSTX_PHY_RX_LD_VAL, RDPCS_PHY_RX_REF_LD_VAL, mask_sh),\
> + LE_SF(RDPCSTX0_RDPCSTX_PHY_RX_LD_VAL, RDPCS_PHY_RX_VCO_LD_VAL, mask_sh),\
> + LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL6, RDPCS_PHY_DPALT_DISABLE_ACK, mask_sh),\
> + LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL6, RDPCS_PHY_DP_TX0_PSTATE, mask_sh),\
> + LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL6, RDPCS_PHY_DP_TX1_PSTATE, mask_sh),\
> + LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL6, RDPCS_PHY_DP_TX0_MPLL_EN, mask_sh),\
> + LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL6, RDPCS_PHY_DP_TX1_MPLL_EN, mask_sh),\
> + LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL6, RDPCS_PHY_DP_REF_CLK_EN, mask_sh),\
> + LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL5, RDPCS_PHY_DP_TX2_WIDTH, mask_sh),\
> + LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL5, RDPCS_PHY_DP_TX2_RATE, mask_sh),\
> + LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL5, RDPCS_PHY_DP_TX3_WIDTH, mask_sh),\
> + LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL5, RDPCS_PHY_DP_TX3_RATE, mask_sh),\
> + LE_SF(DCIO_SOFT_RESET, UNIPHYA_SOFT_RESET, mask_sh),\
> + LE_SF(DCIO_SOFT_RESET, UNIPHYB_SOFT_RESET, mask_sh),\
> + LE_SF(DCIO_SOFT_RESET, UNIPHYC_SOFT_RESET, mask_sh),\
> + LE_SF(DCIO_SOFT_RESET, UNIPHYD_SOFT_RESET, mask_sh),\
> + LE_SF(DCIO_SOFT_RESET, UNIPHYE_SOFT_RESET, mask_sh)
>
> #define LINK_ENCODER_MASK_SH_LIST_DCN20(mask_sh)\
> LINK_ENCODER_MASK_SH_LIST_DCN10(mask_sh),\
> @@ -63,6 +198,49 @@
> SRI(CLOCK_ENABLE, SYMCLK, id), \
> SRI(CHANNEL_XBAR_CNTL, UNIPHY, id)
>
> +#define DPCS_DCN2_CMN_REG_LIST(id) \
> + SRI(DIG_LANE_ENABLE, DIG, id), \
> + SRI(TMDS_CTL_BITS, DIG, id), \
> + SRI(RDPCSTX_PHY_CNTL3, RDPCSTX, id), \
> + SRI(RDPCSTX_PHY_CNTL4, RDPCSTX, id), \
> + SRI(RDPCSTX_PHY_CNTL5, RDPCSTX, id), \
> + SRI(RDPCSTX_PHY_CNTL6, RDPCSTX, id), \
> + SRI(RDPCSTX_PHY_CNTL7, RDPCSTX, id), \
> + SRI(RDPCSTX_PHY_CNTL8, RDPCSTX, id), \
> + SRI(RDPCSTX_PHY_CNTL9, RDPCSTX, id), \
> + SRI(RDPCSTX_PHY_CNTL10, RDPCSTX, id), \
> + SRI(RDPCSTX_PHY_CNTL11, RDPCSTX, id), \
> + SRI(RDPCSTX_PHY_CNTL12, RDPCSTX, id), \
> + SRI(RDPCSTX_PHY_CNTL13, RDPCSTX, id), \
> + SRI(RDPCSTX_PHY_CNTL14, RDPCSTX, id), \
> + SRI(RDPCSTX_CNTL, RDPCSTX, id), \
> + SRI(RDPCSTX_CLOCK_CNTL, RDPCSTX, id), \
> + SRI(RDPCSTX_INTERRUPT_CONTROL, RDPCSTX, id), \
> + SRI(RDPCSTX_PHY_CNTL0, RDPCSTX, id), \
> + SRI(RDPCSTX_PHY_CNTL2, RDPCSTX, id), \
> + SRI(RDPCSTX_PLL_UPDATE_DATA, RDPCSTX, id), \
> + SRI(RDPCS_TX_CR_ADDR, RDPCSTX, id), \
> + SRI(RDPCS_TX_CR_DATA, RDPCSTX, id), \
> + SRI(RDPCSTX_PHY_FUSE0, RDPCSTX, id), \
> + SRI(RDPCSTX_PHY_FUSE1, RDPCSTX, id), \
> + SRI(RDPCSTX_PHY_FUSE2, RDPCSTX, id), \
> + SRI(RDPCSTX_PHY_FUSE3, RDPCSTX, id), \
> + SRI(DPCSTX_TX_CLOCK_CNTL, DPCSTX, id), \
> + SRI(DPCSTX_TX_CNTL, DPCSTX, id), \
> + SRI(DPCSTX_DEBUG_CONFIG, DPCSTX, id), \
> + SRI(RDPCSTX_DEBUG_CONFIG, RDPCSTX, id), \
> + SR(RDPCSTX0_RDPCSTX_SCRATCH)
> +
> +
> +#define DPCS_DCN2_REG_LIST(id) \
> + DPCS_DCN2_CMN_REG_LIST(id), \
> + SRI(RDPCSTX_PHY_RX_LD_VAL, RDPCSTX, id),\
> + SRI(RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG, RDPCSTX, id)
> +
> +#define LE_DCN2_REG_LIST(id) \
> + LE_DCN10_REG_LIST(id), \
> + SR(DCIO_SOFT_RESET)
> +
> struct mpll_cfg {
> uint32_t mpllb_ana_v2i;
> uint32_t mpllb_ana_freq_vco;
> diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
> index cfc6991..186277d 100644
> --- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
> +++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
> @@ -65,6 +65,8 @@
>
> #include "dcn/dcn_2_0_0_offset.h"
> #include "dcn/dcn_2_0_0_sh_mask.h"
> +#include "dpcs/dpcs_2_0_0_offset.h"
> +#include "dpcs/dpcs_2_0_0_sh_mask.h"
>
> #include "nbio/nbio_2_3_offset.h"
>
> @@ -548,6 +550,7 @@ static const struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[] = {
> [id] = {\
> LE_DCN10_REG_LIST(id), \
> UNIPHY_DCN2_REG_LIST(phyid), \
> + DPCS_DCN2_REG_LIST(id), \
> SRI(DP_DPHY_INTERNAL_CTRL, DP, id) \
> }
>
> @@ -561,11 +564,13 @@ static const struct dcn10_link_enc_registers link_enc_regs[] = {
> };
>
> static const struct dcn10_link_enc_shift le_shift = {
> - LINK_ENCODER_MASK_SH_LIST_DCN20(__SHIFT)
> + LINK_ENCODER_MASK_SH_LIST_DCN20(__SHIFT),\
> + DPCS_DCN2_MASK_SH_LIST(__SHIFT)
> };
>
> static const struct dcn10_link_enc_mask le_mask = {
> - LINK_ENCODER_MASK_SH_LIST_DCN20(_MASK)
> + LINK_ENCODER_MASK_SH_LIST_DCN20(_MASK),\
> + DPCS_DCN2_MASK_SH_LIST(_MASK)
> };
>
> #define ipp_regs(id)\
> diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_link_encoder.h b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_link_encoder.h
> index 1d7a1a5..033d5d7 100644
> --- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_link_encoder.h
> +++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_link_encoder.h
> @@ -33,6 +33,45 @@ struct dcn21_link_encoder {
> struct dpcssys_phy_seq_cfg phy_seq_cfg;
> };
>
> +#define DPCS_DCN21_MASK_SH_LIST(mask_sh)\
> + DPCS_DCN2_MASK_SH_LIST(mask_sh),\
> + LE_SF(RDPCSTX0_RDPCSTX_PHY_FUSE3, RDPCS_PHY_TX_VBOOST_LVL, mask_sh),\
> + LE_SF(RDPCSTX0_RDPCSTX_PHY_FUSE2, RDPCS_PHY_DP_MPLLB_CP_PROP_GS, mask_sh),\
> + LE_SF(RDPCSTX0_RDPCSTX_PHY_FUSE0, RDPCS_PHY_RX_VREF_CTRL, mask_sh),\
> + LE_SF(RDPCSTX0_RDPCSTX_PHY_FUSE0, RDPCS_PHY_DP_MPLLB_CP_INT_GS, mask_sh),\
> + LE_SF(RDPCSTX0_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG, RDPCS_DMCU_DPALT_DIS_BLOCK_REG, mask_sh),\
> + LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL15, RDPCS_PHY_SUP_PRE_HP, mask_sh),\
> + LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL15, RDPCS_PHY_DP_TX0_VREGDRV_BYP, mask_sh),\
> + LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL15, RDPCS_PHY_DP_TX1_VREGDRV_BYP, mask_sh),\
> + LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL15, RDPCS_PHY_DP_TX2_VREGDRV_BYP, mask_sh),\
> + LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL15, RDPCS_PHY_DP_TX3_VREGDRV_BYP, mask_sh),\
> + LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL6, RDPCS_PHY_DPALT_DP4, mask_sh),\
> + LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL6, RDPCS_PHY_DPALT_DISABLE, mask_sh),\
> + LE_SF(RDPCSTX0_RDPCSTX_PHY_FUSE0, RDPCS_PHY_DP_TX0_EQ_MAIN, mask_sh),\
> + LE_SF(RDPCSTX0_RDPCSTX_PHY_FUSE0, RDPCS_PHY_DP_TX0_EQ_PRE, mask_sh),\
> + LE_SF(RDPCSTX0_RDPCSTX_PHY_FUSE0, RDPCS_PHY_DP_TX0_EQ_POST, mask_sh),\
> + LE_SF(RDPCSTX0_RDPCSTX_PHY_FUSE1, RDPCS_PHY_DP_TX1_EQ_MAIN, mask_sh),\
> + LE_SF(RDPCSTX0_RDPCSTX_PHY_FUSE1, RDPCS_PHY_DP_TX1_EQ_PRE, mask_sh),\
> + LE_SF(RDPCSTX0_RDPCSTX_PHY_FUSE1, RDPCS_PHY_DP_TX1_EQ_POST, mask_sh),\
> + LE_SF(RDPCSTX0_RDPCSTX_PHY_FUSE2, RDPCS_PHY_DP_TX2_EQ_MAIN, mask_sh),\
> + LE_SF(RDPCSTX0_RDPCSTX_PHY_FUSE2, RDPCS_PHY_DP_TX2_EQ_PRE, mask_sh),\
> + LE_SF(RDPCSTX0_RDPCSTX_PHY_FUSE2, RDPCS_PHY_DP_TX2_EQ_POST, mask_sh),\
> + LE_SF(RDPCSTX0_RDPCSTX_PHY_FUSE3, RDPCS_PHY_DP_TX3_EQ_MAIN, mask_sh),\
> + LE_SF(RDPCSTX0_RDPCSTX_PHY_FUSE3, RDPCS_PHY_DCO_FINETUNE, mask_sh),\
> + LE_SF(RDPCSTX0_RDPCSTX_PHY_FUSE3, RDPCS_PHY_DCO_RANGE, mask_sh),\
> + LE_SF(RDPCSTX0_RDPCSTX_PHY_FUSE3, RDPCS_PHY_DP_TX3_EQ_PRE, mask_sh),\
> + LE_SF(RDPCSTX0_RDPCSTX_PHY_FUSE3, RDPCS_PHY_DP_TX3_EQ_POST, mask_sh),\
> + LE_SF(DCIO_SOFT_RESET, UNIPHYA_SOFT_RESET, mask_sh),\
> + LE_SF(DCIO_SOFT_RESET, UNIPHYB_SOFT_RESET, mask_sh),\
> + LE_SF(DCIO_SOFT_RESET, UNIPHYC_SOFT_RESET, mask_sh),\
> + LE_SF(DCIO_SOFT_RESET, UNIPHYD_SOFT_RESET, mask_sh),\
> + LE_SF(DCIO_SOFT_RESET, UNIPHYE_SOFT_RESET, mask_sh)
> +
> +#define DPCS_DCN21_REG_LIST(id) \
> + DPCS_DCN2_REG_LIST(id),\
> + SRI(RDPCSTX_PHY_CNTL15, RDPCSTX, id),\
> + SRI(RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG, RDPCSTX, id)
> +
> #define LINK_ENCODER_MASK_SH_LIST_DCN21(mask_sh)\
> LINK_ENCODER_MASK_SH_LIST_DCN20(mask_sh),\
> LE_SF(UNIPHYA_CHANNEL_XBAR_CNTL, UNIPHY_CHANNEL0_XBAR_SOURCE, mask_sh),\
> diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
> index 8fa6392..caafdc9 100644
> --- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
> +++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
> @@ -60,6 +60,8 @@
>
> #include "dcn20/dcn20_dwb.h"
> #include "dcn20/dcn20_mmhubbub.h"
> +#include "dpcs/dpcs_2_1_0_offset.h"
> +#include "dpcs/dpcs_2_1_0_sh_mask.h"
>
> #include "renoir_ip_offset.h"
> #include "dcn/dcn_2_1_0_offset.h"
> @@ -1495,8 +1497,9 @@ static const struct encoder_feature_support link_enc_feature = {
>
> #define link_regs(id, phyid)\
> [id] = {\
> - LE_DCN10_REG_LIST(id), \
> + LE_DCN2_REG_LIST(id), \
> UNIPHY_DCN2_REG_LIST(phyid), \
> + DPCS_DCN21_REG_LIST(id), \
> SRI(DP_DPHY_INTERNAL_CTRL, DP, id) \
> }
>
> @@ -1535,11 +1538,13 @@ static const struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[] = {
> };
>
> static const struct dcn10_link_enc_shift le_shift = {
> - LINK_ENCODER_MASK_SH_LIST_DCN20(__SHIFT)
> + LINK_ENCODER_MASK_SH_LIST_DCN20(__SHIFT),\
> + DPCS_DCN21_MASK_SH_LIST(__SHIFT)
> };
>
> static const struct dcn10_link_enc_mask le_mask = {
> - LINK_ENCODER_MASK_SH_LIST_DCN20(_MASK)
> + LINK_ENCODER_MASK_SH_LIST_DCN20(_MASK),\
> + DPCS_DCN21_MASK_SH_LIST(_MASK)
> };
>
> static int map_transmitter_id_to_phy_instance(
>
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