[PATCH 2/2] Revert "drm/amdgpu: Fix bugs in setting CP RB/MEC DOORBELL_RANGE registers"

[Alex Deucher]

On Tue, Feb 19, 2019 at 1:47 PM Alex Deucher <alexdeucher at gmail.com> wrote:
>
> On Tue, Feb 19, 2019 at 11:29 AM Zhao, Yong <Yong.Zhao at amd.com> wrote:
> >
> > The original change caused regression, so revert it until the new fix is
> > ready.
> > https://bugs.freedesktop.org/show_bug.cgi?id=109650
>
> Make this:
> Bug: https://bugs.freedesktop.org/show_bug.cgi?id=109650
>
> With that fixed:

With that fixed,  For the series,

> Acked-by: Alex Deucher <alexander.deucher at amd.com>
>
> >
> > This reverts commit 764c85fef41722db0f21558c6c2fb38bee172d19.
> >
> > Change-Id: I6c634d8bdb98efcfdec33581d92f7ba02416061b
> > Signed-off-by: Yong Zhao <Yong.Zhao at amd.com>
> > ---
> >  drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 19 ++++---------------
> >  drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 19 +++++--------------
> >  2 files changed, 9 insertions(+), 29 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
> > index 41cf9d0224d9..b8e50a34bdb3 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
> > @@ -4223,8 +4223,8 @@ static void gfx_v8_0_set_cpg_door_bell(struct amdgpu_device *adev, struct amdgpu
> >                                         adev->doorbell_index.gfx_ring0);
> >         WREG32(mmCP_RB_DOORBELL_RANGE_LOWER, tmp);
> >
> > -       /* There is only one GFX queue */
> > -       WREG32(mmCP_RB_DOORBELL_RANGE_UPPER, tmp);
> > +       WREG32(mmCP_RB_DOORBELL_RANGE_UPPER,
> > +               CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK);
> >  }
> >
> >  static int gfx_v8_0_cp_gfx_resume(struct amdgpu_device *adev)
> > @@ -4646,19 +4646,8 @@ static int gfx_v8_0_kcq_init_queue(struct amdgpu_ring *ring)
> >  static void gfx_v8_0_set_mec_doorbell_range(struct amdgpu_device *adev)
> >  {
> >         if (adev->asic_type > CHIP_TONGA) {
> > -               /* The first few doorbells in pci doorbell bar are for GFX RB
> > -                * rings and all the leftover for MEC.
> > -                * So CP_MEC_DOORBELL_RANGE_LOWER should be set one index after
> > -                * CP_RB_DOORBELL_RANGE_UPPER, as we assume there is only one
> > -                * GFX RB rings.
> > -                */
> > -               u32 tmp = REG_SET_FIELD(0, CP_MEC_DOORBELL_RANGE_LOWER,
> > -                               DOORBELL_RANGE_LOWER,
> > -                               adev->gfx.gfx_ring[0].doorbell_index + 1);
> > -
> > -               WREG32(mmCP_MEC_DOORBELL_RANGE_LOWER, tmp);
> > -               WREG32(mmCP_MEC_DOORBELL_RANGE_UPPER,
> > -                               CP_MEC_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK);
> > +               WREG32(mmCP_MEC_DOORBELL_RANGE_LOWER, adev->doorbell_index.kiq << 2);
> > +               WREG32(mmCP_MEC_DOORBELL_RANGE_UPPER, adev->doorbell_index.mec_ring7 << 2);
> >         }
> >         /* enable doorbells */
> >         WREG32_FIELD(CP_PQ_STATUS, DOORBELL_ENABLE, 1);
> > diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> > index 36f417fd6ba9..5533f6e4f4a4 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> > @@ -2631,8 +2631,8 @@ static int gfx_v9_0_cp_gfx_resume(struct amdgpu_device *adev)
> >                         DOORBELL_RANGE_LOWER, ring->doorbell_index);
> >         WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_LOWER, tmp);
> >
> > -       /* There is only one GFX queue */
> > -       WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_UPPER, tmp);
> > +       WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_UPPER,
> > +                      CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK);
> >
> >
> >         /* start the ring */
> > @@ -2995,19 +2995,10 @@ static int gfx_v9_0_kiq_init_register(struct amdgpu_ring *ring)
> >
> >         /* enable the doorbell if requested */
> >         if (ring->use_doorbell) {
> > -               /* The first few doorbells in pci doorbell bar are for GFX RB
> > -                * rings and all the leftover for MEC.
> > -                * So CP_MEC_DOORBELL_RANGE_LOWER should be set one index after
> > -                * CP_RB_DOORBELL_RANGE_UPPER, as we assume there is only one
> > -                * GFX RB rings.
> > -                */
> > -               u32 tmp = REG_SET_FIELD(0, CP_MEC_DOORBELL_RANGE_LOWER,
> > -                               DOORBELL_RANGE_LOWER,
> > -                               adev->gfx.gfx_ring[0].doorbell_index + 2);
> > -
> > -               WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_LOWER, tmp);
> > +               WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_LOWER,
> > +                                       (adev->doorbell_index.kiq * 2) << 2);
> >                 WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_UPPER,
> > -                               CP_MEC_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK);
> > +                                       (adev->doorbell_index.userqueue_end * 2) << 2);
> >         }
> >
> >         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL,
> > --
> > 2.17.1
> >
> > _______________________________________________
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