[PATCH] drm/amd/display: Include names of all PP clock types

Alex Deucher alexdeucher at gmail.com
Mon Jan 14 17:47:44 UTC 2019


On Sun, Jan 13, 2019 at 8:24 AM Rafał Miłecki <zajec5 at gmail.com> wrote:
>
> From: Rafał Miłecki <rafal at milecki.pl>
>
> This fixes printing clock names in cases like:
> [    5.352311] [drm] DM_PPLIB: values for Invalid clock
> [    5.352313] [drm] DM_PPLIB:   400000 in kHz
> [    5.352313] [drm] DM_PPLIB:   933000 in kHz
> [    5.352314] [drm] DM_PPLIB:   1067000 in kHz
> [    5.352315] [drm] DM_PPLIB:   1200000 in kHz
> [    5.352317] [drm] DM_PPLIB: values for Invalid clock
> [    5.352318] [drm] DM_PPLIB:   300000 in kHz
> [    5.352318] [drm] DM_PPLIB:   600000 in kHz
> [    5.352319] [drm] DM_PPLIB:   626000 in kHz
> [    5.352320] [drm] DM_PPLIB:   654000 in kHz
> (source: HP EliteBook 745 G5 w. RAVEN 0x1002:0x15DD 0x103C:0x83D5 0xD1)
>
> On my system above "Invalid" names got replaced by "F" and "DCF".
>
> The same problem was occurring on Huawei Matebook D with just 667000 kHz
> instead of 400000 kHz.
>
> Signed-off-by: Rafał Miłecki <rafal at milecki.pl>

Applied.  thanks!

Alex

> ---
>  drivers/gpu/drm/amd/display/dc/dm_services_types.h | 10 +++++++++-
>  1 file changed, 9 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/display/dc/dm_services_types.h b/drivers/gpu/drm/amd/display/dc/dm_services_types.h
> index 1af8c777b3ac..9afd36a031a9 100644
> --- a/drivers/gpu/drm/amd/display/dc/dm_services_types.h
> +++ b/drivers/gpu/drm/amd/display/dc/dm_services_types.h
> @@ -82,7 +82,15 @@ enum dm_pp_clock_type {
>  #define DC_DECODE_PP_CLOCK_TYPE(clk_type) \
>         (clk_type) == DM_PP_CLOCK_TYPE_DISPLAY_CLK ? "Display" : \
>         (clk_type) == DM_PP_CLOCK_TYPE_ENGINE_CLK ? "Engine" : \
> -       (clk_type) == DM_PP_CLOCK_TYPE_MEMORY_CLK ? "Memory" : "Invalid"
> +       (clk_type) == DM_PP_CLOCK_TYPE_MEMORY_CLK ? "Memory" : \
> +       (clk_type) == DM_PP_CLOCK_TYPE_DCFCLK ? "DCF" : \
> +       (clk_type) == DM_PP_CLOCK_TYPE_DCEFCLK ? "DCEF" : \
> +       (clk_type) == DM_PP_CLOCK_TYPE_SOCCLK ? "SoC" : \
> +       (clk_type) == DM_PP_CLOCK_TYPE_PIXELCLK ? "Pixel" : \
> +       (clk_type) == DM_PP_CLOCK_TYPE_DISPLAYPHYCLK ? "Display PHY" : \
> +       (clk_type) == DM_PP_CLOCK_TYPE_DPPCLK ? "DPP" : \
> +       (clk_type) == DM_PP_CLOCK_TYPE_FCLK ? "F" : \
> +       "Invalid"
>
>  #define DM_PP_MAX_CLOCK_LEVELS 8
>
> --
> 2.20.1
>


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