[RFC PATCH] drm: disable WC optimization for cache coherent devices on non-x86
hch at infradead.org
Mon Jan 21 16:22:38 UTC 2019
On Mon, Jan 21, 2019 at 05:14:37PM +0100, Ard Biesheuvel wrote:
> > I'll add big fat comments. But the fact that nothing is exported
> > there should be a fairly big hint.
> I don't follow. How do other header files 'export' things in a way
> that this header doesn't?
Well, I'll add comments to make it more obvious..
> As far as I can tell, these drivers allocate DMA'able memory [in
> ttm_tt_populate()] and subsequently create their own CPU mappings for
> it, assuming that
> a) the default is cache coherent, so vmap()ing those pages with
> cacheable attributes works, and
Yikes. vmaping with different attributes is generally prone to
create problems on a lot of architectures.
> b) telling the GPU to use NoSnoop attributes makes the accesses it
> performs coherent with non-cacheable CPU mappings of those physical
> Since the latter is not true for many arm64 systems, I need this patch
> to get a working system.
Do we know that this actually works anywhere but x86?
In general I would call these above sequence rather bogus and would
prefer we could get rid of such antipatterns in the kernel and just use
dma_alloc_attrs with DMA_ATTR_WRITECOMBINE if we want writecombine
Until that happens we should just change the driver ifdefs to default
the hacks to off and only enable them on setups where we 100%
positively know that they actually work. And document that fact
in big fat comments.
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