[RFC PATCH] drm: disable WC optimization for cache coherent devices on non-x86

Michel Dänzer michel at daenzer.net
Thu Jan 24 09:31:06 UTC 2019

On 2019-01-23 5:52 p.m., Ard Biesheuvel wrote:
> On Wed, 23 Jan 2019 at 17:44, Christoph Hellwig <hch at infradead.org> wrote:
>> I think we just want a driver-local check for those combinations
>> where we know this hack actually works, which really just seems
>> to be x86-64 with PAT. Something like the patch below, but maybe with
>> even more strong warnings to not do something like this elsewhere:
> I agree that your patch seems like the right way to ensure that the WC
> optimization hack is only used where we know it works.
> But my concern is that it seems likely that non-cache coherent
> implementations are relying on this hack as well.

I've been trying to tell you they can't rely on that, because the amdgpu
driver doesn't use this functionality for fundamentals such as ring
buffers used for feeding the hardware with commands. Instead, for those
it relies on snooped PCIe transfers being coherent with the CPU caches.

>> -#elif defined(CONFIG_X86) && !defined(CONFIG_X86_PAT)
>> -       /* Don't try to enable write-combining when it can't work, or things
>> -        * may be slow
>> -        * See https://bugs.freedesktop.org/show_bug.cgi?id=88758
>> -        */
>> -
>> -#warning Please enable CONFIG_MTRR and CONFIG_X86_PAT for better performance \
>> -        thanks to write-combining
>> -#endif
>> -
>> -       if (bo->flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC)
>> -               DRM_INFO_ONCE("Please enable CONFIG_MTRR and CONFIG_X86_PAT for "
>> -                             "better performance thanks to write-combining\n");

FWIW, please don't drop these compile and build time warnings where we
continue to take advantage of PAT.

Earthling Michel Dänzer               |               http://www.amd.com
Libre software enthusiast             |             Mesa and X developer

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