[RFC PATCH] drm: disable WC optimization for cache coherent devices on non-x86

Koenig, Christian Christian.Koenig at amd.com
Thu Jan 24 11:23:44 UTC 2019

Am 24.01.19 um 10:59 schrieb Ard Biesheuvel:
> [SNIP]
> This is *exactly* my point the whole time.
> The current code has
> static inline bool drm_arch_can_wc_memory(void)
> {
> #if defined(CONFIG_PPC) && !defined(CONFIG_NOT_COHERENT_CACHE)
>     return false;
> which means the optimization is disabled *unless the system is
> non-cache coherent*
> So if you have reports that the optimization works on some PowerPC, it
> must be non-cache coherent PowerPC, because that is the only place
> where it is enabled in the first place.
>> The only problematic here actually seems to be ARM, so you should
>> probably just add an "#ifdef .._ARM return false;".
> ARM/arm64 does not have a Kconfig symbol like
> CONFIG_NOT_COHERENT_CACHE, so we can only disable it everywhere. If
> there are non-coherent ARM systems that are currently working in the
> same way as those non-coherent PowerPC systems, we will break them by
> doing this.

Summing the things I've read so far for ARM up I actually think it 
depends on a runtime configuration and not on compile time one.

So the whole idea of providing the device to the drm_*_can_wc_memory() 
function isn't so far fetched.

But for now I do prefer working and slightly slower system over broken 
one, so I think we should just disable this on ARM for now.


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