[PATCH 126/138] drm/amd/powerplay: add sys interface for pcie for smu

[Huang Rui]

From: Likun Gao <Likun.Gao at amd.com>

Add sys interface for set/get PCIE info for SMU.
The related operate will do nothing as vega20 do not support it now.

Signed-off-by: Likun Gao <Likun.Gao at amd.com>
Reviewed-by: Huang Rui <ray.huang at amd.com>
Reviewed-by: Kevin Wang <kevin1.wang at amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c     | 8 ++++++--
 drivers/gpu/drm/amd/powerplay/vega20_ppt.c | 6 ++++++
 2 files changed, 12 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
index a9e1410..baff3b9 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
@@ -1005,7 +1005,9 @@ static ssize_t amdgpu_get_pp_dpm_pcie(struct device *dev,
 	struct drm_device *ddev = dev_get_drvdata(dev);
 	struct amdgpu_device *adev = ddev->dev_private;
 
-	if (adev->powerplay.pp_funcs->print_clock_levels)
+	if (is_support_sw_smu(adev))
+		return smu_print_clk_levels(&adev->smu, PP_PCIE, buf);
+	else if (adev->powerplay.pp_funcs->print_clock_levels)
 		return amdgpu_dpm_print_clock_levels(adev, PP_PCIE, buf);
 	else
 		return snprintf(buf, PAGE_SIZE, "\n");
@@ -1025,7 +1027,9 @@ static ssize_t amdgpu_set_pp_dpm_pcie(struct device *dev,
 	if (ret)
 		return ret;
 
-	if (adev->powerplay.pp_funcs->force_clock_level)
+	if (is_support_sw_smu(adev))
+		ret = smu_force_clk_levels(&adev->smu, PP_PCIE, mask);
+	else if (adev->powerplay.pp_funcs->force_clock_level)
 		ret = amdgpu_dpm_force_clock_level(adev, PP_PCIE, mask);
 
 	if (ret)
diff --git a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
index 14185bc..dff5d83 100644
--- a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
@@ -775,6 +775,9 @@ static int vega20_print_clk_levels(struct smu_context *smu,
 				? "*" : "");
 		break;
 
+	case PP_PCIE:
+		break;
+
 	case OD_SCLK:
 		if (od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMIN].feature_id &&
 		    od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMAX].feature_id) {
@@ -1016,6 +1019,9 @@ static int vega20_force_clk_levels(struct smu_context *smu,
 
 		break;
 
+	case PP_PCIE:
+		break;
+
 	default:
 		break;
 	}
-- 
2.7.4