[PATCH 1/2] drm/amdgpu/gfx9: use reset default for PA_SC_FIFO_SIZE

Yuan, Xiaojie Xiaojie.Yuan at amd.com
Tue Jul 2 02:29:44 UTC 2019


Reviewed-by: Xiaojie Yuan <xiaojie.yuan at amd.com>

BR,
Xiaojie

________________________________________
From: amd-gfx <amd-gfx-bounces at lists.freedesktop.org> on behalf of Alex Deucher <alexdeucher at gmail.com>
Sent: Monday, July 1, 2019 10:00 PM
To: amd-gfx at lists.freedesktop.org
Cc: Deucher, Alexander
Subject: [PATCH 1/2] drm/amdgpu/gfx9: use reset default for PA_SC_FIFO_SIZE

Recommended by the hw team.

Signed-off-by: Alex Deucher <alexander.deucher at amd.com>
---
 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 19 -------------------
 1 file changed, 19 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index 9b413f6fa588..5bdd7c42b00e 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -1960,25 +1960,6 @@ static void gfx_v9_0_constants_init(struct amdgpu_device *adev)
        mutex_unlock(&adev->srbm_mutex);

        gfx_v9_0_init_compute_vmid(adev);
-
-       mutex_lock(&adev->grbm_idx_mutex);
-       /*
-        * making sure that the following register writes will be broadcasted
-        * to all the shaders
-        */
-       gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
-
-       WREG32_SOC15_RLC(GC, 0, mmPA_SC_FIFO_SIZE,
-                  (adev->gfx.config.sc_prim_fifo_size_frontend <<
-                       PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE__SHIFT) |
-                  (adev->gfx.config.sc_prim_fifo_size_backend <<
-                       PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE__SHIFT) |
-                  (adev->gfx.config.sc_hiz_tile_fifo_size <<
-                       PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE__SHIFT) |
-                  (adev->gfx.config.sc_earlyz_tile_fifo_size <<
-                       PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE__SHIFT));
-       mutex_unlock(&adev->grbm_idx_mutex);
-
 }

 static void gfx_v9_0_wait_for_rlc_serdes(struct amdgpu_device *adev)
--
2.20.1

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