[PATCH 08/17] drm/amdgpu: add function to start jpeg enc block

[boyuan.zhang at amd.com]

From: Boyuan Zhang <boyuan.zhang at amd.com>

Start jpeg encode block, set system interrupt, and initialize registers.

Signed-off-by: Boyuan Zhang <boyuan.zhang at amd.com>
Reviewed-by: Alex Deucher <alexander.deucher at amd.com>
---
 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c | 33 +++++++++++++++++++++++++++
 1 file changed, 33 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
index cb77554cc692..8e25f83333f1 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
@@ -612,6 +612,37 @@ static int jpeg_v2_0_start(struct amdgpu_device *adev)
 	return 0;
 }
 
+/**
+ * jpeg_enc_v2_0_start - start JPEG ENC block
+ *
+ * @adev: amdgpu_device pointer
+ *
+ * Setup and start the JPEG ENC block
+ */
+static int jpeg_enc_v2_0_start(struct amdgpu_device *adev)
+{
+	struct amdgpu_ring *ring = &adev->vcn.ring_jpeg_enc;
+
+	/* enable System Interrupt for JRBC ENC */
+	WREG32_P(SOC15_REG_OFFSET(VCN, 0, mmJPEG_SYS_INT_EN),
+		JPEG_SYS_INT_EN__EJRBC_MASK,
+		~JPEG_SYS_INT_EN__EJRBC_MASK);
+
+	WREG32_SOC15(UVD, 0, mmUVD_JMI_ENC_JRBC_RB_VMID, 0);
+	WREG32_SOC15(UVD, 0, mmUVD_JRBC_ENC_RB_CNTL, (0x00000001L | 0x00000002L));
+	WREG32_SOC15(UVD, 0, mmUVD_LMI_EJRBC_RB_64BIT_BAR_LOW,
+		lower_32_bits(ring->gpu_addr));
+	WREG32_SOC15(UVD, 0, mmUVD_LMI_EJRBC_RB_64BIT_BAR_HIGH,
+		upper_32_bits(ring->gpu_addr));
+	WREG32_SOC15(UVD, 0, mmUVD_JRBC_ENC_RB_RPTR, 0);
+	WREG32_SOC15(UVD, 0, mmUVD_JRBC_ENC_RB_WPTR, 0);
+	WREG32_SOC15(UVD, 0, mmUVD_JRBC_ENC_RB_CNTL, 0x00000002L);
+	WREG32_SOC15(UVD, 0, mmUVD_JRBC_ENC_RB_SIZE, ring->ring_size / 4);
+	ring->wptr = RREG32_SOC15(UVD, 0, mmUVD_JRBC_ENC_RB_WPTR);
+
+	return 0;
+}
+
 /**
  * jpeg_v2_0_stop - stop JPEG block
  *
@@ -975,6 +1006,8 @@ static int vcn_v2_0_start(struct amdgpu_device *adev)
 
 	r = jpeg_v2_0_start(adev);
 
+	r = jpeg_enc_v2_0_start(adev);
+
 	return r;
 }
 
-- 
2.17.1