[PATCH 1/3] drm/amd/powerplay: add helper of smu_feature_dpmclk_check for smu

[Quan, Evan]

Please rename smu_feature_dpmclk_check as smu_is_clk_dpm_enabled or other more meaningful.

> +	switch (clk_type) {
> +	case SMU_MCLK:
> +	case SMU_UCLK:
> +		if (!smu_feature_is_enabled(smu,
> SMU_FEATURE_DPM_UCLK_BIT)) {
> +			pr_warn("uclk dpm is not enabled\n");
> +			ret = -EACCES;
> +		}
> +		break;
> +	case SMU_GFXCLK:
> +	case SMU_SCLK:
> +		if (!smu_feature_is_enabled(smu,
> SMU_FEATURE_DPM_GFXCLK_BIT)) {
> +			pr_warn("gfxclk dpm is not enabled\n");
> +			ret = -EACCES;
> +		}
> +	case SMU_SOCCLK:
> +		if (!smu_feature_is_enabled(smu,
> SMU_FEATURE_DPM_SOCCLK_BIT)) {
> +			pr_warn("sockclk dpm is not enabled\n");
> +			ret = -EACCES;
> +		}
> +		break;
> +	default:
> +		ret = 0;
> +		break;
> +	}
> +
> +	return ret;
> +}
> +

The code logic can be simplied as
switch (clk_type) {
	case SMU_MCLK:
	case SMU_UCLK:
                                  Clk_id = SMU_FEATURE_DPM_UCLK_BIT;
                                   Break;
	case SMU_GFXCLK:
	case SMU_SCLK:
                                    clk_id = SMU_FEATURE_DPM_GFXCLK_BIT;
                                    break;
......
}
if (!smu_feature_is_enabled(smu, clk_id)) {
			pr_warn("gfxclk dpm is not enabled\n");
			return 0;
}

Regards,
Evan
> -----Original Message-----
> From: Wang, Kevin(Yang) <Kevin1.Wang at amd.com>
> Sent: Friday, July 12, 2019 5:15 PM
> To: amd-gfx at lists.freedesktop.org
> Cc: Feng, Kenneth <Kenneth.Feng at amd.com>; Quan, Evan
> <Evan.Quan at amd.com>; Xu, Feifei <Feifei.Xu at amd.com>; Wang,
> Kevin(Yang) <Kevin1.Wang at amd.com>
> Subject: [PATCH 1/3] drm/amd/powerplay: add helper of
> smu_feature_dpmclk_check for smu
> 
> add this helper function to check dpm clk feature is enabled.
> 
> Change-Id: I51a4e9246d83d74a8e687fbc45983848adc960ca
> Signed-off-by: Kevin Wang <kevin1.wang at amd.com>
> ---
>  drivers/gpu/drm/amd/powerplay/amdgpu_smu.c    | 71 +++++++++++++---
> ---
>  .../gpu/drm/amd/powerplay/inc/amdgpu_smu.h    |  1 +
>  2 files changed, 49 insertions(+), 23 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
> b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
> index da4332d2dbbc..be90ae59dfa8 100644
> --- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
> +++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
> @@ -68,6 +68,10 @@ int smu_set_soft_freq_range(struct smu_context
> *smu, enum smu_clk_type clk_type,
>  	if (min <= 0 && max <= 0)
>  		return -EINVAL;
> 
> +	ret = smu_feature_dpmclk_check(smu, clk_type);
> +	if (ret)
> +		return ret;
> +
>  	clk_id = smu_clk_get_index(smu, clk_type);
>  	if (clk_id < 0)
>  		return clk_id;
> @@ -101,6 +105,10 @@ int smu_set_hard_freq_range(struct smu_context
> *smu, enum smu_clk_type clk_type,
>  	if (min <= 0 && max <= 0)
>  		return -EINVAL;
> 
> +	ret = smu_feature_dpmclk_check(smu, clk_type);
> +	if (ret)
> +		return ret;
> +
>  	clk_id = smu_clk_get_index(smu, clk_type);
>  	if (clk_id < 0)
>  		return clk_id;
> @@ -134,29 +142,9 @@ int smu_get_dpm_freq_range(struct smu_context
> *smu, enum smu_clk_type clk_type,
>  	if (!min && !max)
>  		return -EINVAL;
> 
> -	switch (clk_type) {
> -	case SMU_MCLK:
> -	case SMU_UCLK:
> -		if (!smu_feature_is_enabled(smu,
> SMU_FEATURE_DPM_UCLK_BIT)) {
> -			pr_warn("uclk dpm is not enabled\n");
> -			return 0;
> -		}
> -		break;
> -	case SMU_GFXCLK:
> -	case SMU_SCLK:
> -		if (!smu_feature_is_enabled(smu,
> SMU_FEATURE_DPM_GFXCLK_BIT)) {
> -			pr_warn("gfxclk dpm is not enabled\n");
> -			return 0;
> -		}
> -	case SMU_SOCCLK:
> -		if (!smu_feature_is_enabled(smu,
> SMU_FEATURE_DPM_SOCCLK_BIT)) {
> -			pr_warn("sockclk dpm is not enabled\n");
> -			return 0;
> -		}
> -		break;
> -	default:
> -		break;
> -	}
> +	ret = smu_feature_dpmclk_check(smu, clk_type);
> +	if (ret)
> +		return ret;
> 
>  	mutex_lock(&smu->mutex);
>  	clk_id = smu_clk_get_index(smu, clk_type); @@ -199,6 +187,10 @@
> int smu_get_dpm_freq_by_index(struct smu_context *smu, enum
> smu_clk_type clk_typ
>  	if (!value)
>  		return -EINVAL;
> 
> +	ret = smu_feature_dpmclk_check(smu, clk_type);
> +	if (ret)
> +		return ret;
> +
>  	clk_id = smu_clk_get_index(smu, clk_type);
>  	if (clk_id < 0)
>  		return clk_id;
> @@ -227,6 +219,39 @@ int smu_get_dpm_level_count(struct smu_context
> *smu, enum smu_clk_type clk_type,
>  	return smu_get_dpm_freq_by_index(smu, clk_type, 0xff, value);  }
> 
> +int smu_feature_dpmclk_check(struct smu_context *smu, enum
> smu_clk_type
> +clk_type) {
> +	int ret = 0;
> +
> +	switch (clk_type) {
> +	case SMU_MCLK:
> +	case SMU_UCLK:
> +		if (!smu_feature_is_enabled(smu,
> SMU_FEATURE_DPM_UCLK_BIT)) {
> +			pr_warn("uclk dpm is not enabled\n");
> +			ret = -EACCES;
> +		}
> +		break;
> +	case SMU_GFXCLK:
> +	case SMU_SCLK:
> +		if (!smu_feature_is_enabled(smu,
> SMU_FEATURE_DPM_GFXCLK_BIT)) {
> +			pr_warn("gfxclk dpm is not enabled\n");
> +			ret = -EACCES;
> +		}
> +	case SMU_SOCCLK:
> +		if (!smu_feature_is_enabled(smu,
> SMU_FEATURE_DPM_SOCCLK_BIT)) {
> +			pr_warn("sockclk dpm is not enabled\n");
> +			ret = -EACCES;
> +		}
> +		break;
> +	default:
> +		ret = 0;
> +		break;
> +	}
> +
> +	return ret;
> +}
> +
> +
>  int smu_dpm_set_power_gate(struct smu_context *smu, uint32_t
> block_type,
>  			   bool gate)
>  {
> diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
> b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
> index c97324ef7db2..0fbc8f489a49 100644
> --- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
> +++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
> @@ -973,5 +973,6 @@ int smu_set_hard_freq_range(struct smu_context
> *smu, enum smu_clk_type clk_type,  enum amd_dpm_forced_level
> smu_get_performance_level(struct smu_context *smu);  int
> smu_force_performance_level(struct smu_context *smu, enum
> amd_dpm_forced_level level);  int smu_set_display_count(struct
> smu_context *smu, uint32_t count);
> +int smu_feature_dpmclk_check(struct smu_context *smu, enum
> smu_clk_type
> +clk_type);
> 
>  #endif
> --
> 2.22.0